From c378d32c85cc8763355901dd47612f4451842a55 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Fri, 7 Sep 2012 19:51:41 -0400
Subject: [PATCH] Fix parameter pins interspersed with cells broke in 3.840.

---
 Changes                          |  5 +++++
 src/V3LinkDot.cpp                |  3 +++
 test_regress/t/t_inst_prepost.pl | 14 ++++++++++++++
 test_regress/t/t_inst_prepost.v  | 32 ++++++++++++++++++++++++++++++++
 4 files changed, 54 insertions(+)
 create mode 100755 test_regress/t/t_inst_prepost.pl
 create mode 100644 test_regress/t/t_inst_prepost.v

diff --git a/Changes b/Changes
index e2a39ea8a..deb9a126d 100644
--- a/Changes
+++ b/Changes
@@ -3,6 +3,11 @@ Revision history for Verilator
 The contributors that suggested a given feature are shown in [].  [by ...]
 indicates the contributor was also the author of the fix; Thanks!
 
+* Verilator 3.84** devel
+
+****  Fix parameter pins interspersed with cells broke in 3.840.  [Bernard Deadman]
+
+
 * Verilator 3.841 2012/09/03
 
 ***   Add --savable to support model save/restore.  [Jeremy Bennett]
diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp
index cb4233c55..e72fdf829 100644
--- a/src/V3LinkDot.cpp
+++ b/src/V3LinkDot.cpp
@@ -154,6 +154,7 @@ public:
 	    // See t_gen_forif.v for an example.
 	} else {
 	    preErrorDump();
+	    UINFO(4,"name "<<name<<endl);  // Not always same as nodep->name
 	    UINFO(4,"Var1 "<<nodep<<endl);
 	    UINFO(4,"Var2 "<<fnodep<<endl);
 	    if (nodep->type() == fnodep->type()) {
@@ -497,6 +498,7 @@ private:
 	AstBegin* oldbeginp = m_beginp;
 	VSymEnt* oldModSymp = m_modSymp;
 	VSymEnt* oldCurSymp = m_curSymp;
+	int oldParamNum = m_paramNum;
 	// Where do we add it?
 	VSymEnt* aboveSymp = m_curSymp;
 	string origname = AstNode::dedotName(nodep->name());
@@ -522,6 +524,7 @@ private:
 	m_beginp = oldbeginp;
 	m_modSymp = oldModSymp;
 	m_curSymp = oldCurSymp;
+	m_paramNum = oldParamNum;
     }
     virtual void visit(AstCellInline* nodep, AstNUser*) {
 	UINFO(5,"   CELLINLINE under "<<m_scope<<" is "<<nodep<<endl);
diff --git a/test_regress/t/t_inst_prepost.pl b/test_regress/t/t_inst_prepost.pl
new file mode 100755
index 000000000..385b6a57e
--- /dev/null
+++ b/test_regress/t/t_inst_prepost.pl
@@ -0,0 +1,14 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_inst_prepost.v b/test_regress/t/t_inst_prepost.v
new file mode 100644
index 000000000..a00ecf957
--- /dev/null
+++ b/test_regress/t/t_inst_prepost.v
@@ -0,0 +1,32 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2012 by Wilson Snyder.
+
+module t;
+   sub #(10,11,12,13) sub ();
+
+endmodule
+
+module  sub ();
+   parameter A = 0;
+   parameter B = 1;
+
+   ip ip();
+
+   parameter C = 2;
+   parameter D = 3;
+
+   initial begin
+      if (A!=10) $stop;
+      if (B!=11) $stop;
+      if (C!=12) $stop;
+      if (D!=13) $stop;
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule
+
+module ip;
+endmodule