Fix change detection over unpacked arrays.

include/verilated_types.h

@@ -923,12 +923,9 @@ template <class T_Value, std::size_t T_Depth> struct VlUnpacked final {
     T_Value& operator[](size_t index) { return m_storage[index]; }
     const T_Value& operator[](size_t index) const { return m_storage[index]; }
 
-    bool operator!=(const VlUnpacked<T_Value, T_Depth>& that) const {
+    // *this != that, which might be used for change detection/trigger computation, but avoid
-        for (int i = 0; i < T_Depth; ++i) {
+    // operator overloading in VlUnpacked for safety in other contexts.
-            if (m_storage[i] != that.m_storage[i]) return true;
+    inline bool neq(const VlUnpacked<T_Value, T_Depth>& that) const { return neq(*this, that); }
-        }
-        return false;
-    }
 
     // Dumping. Verilog: str = $sformatf("%p", assoc)
     std::string to_string() const {
@@ -940,6 +937,22 @@ template <class T_Value, std::size_t T_Depth> struct VlUnpacked final {
         }
         return out + "} ";
     }
+
+private:
+    template <typename T_Val, std::size_t T_Dep>
+    static bool neq(const VlUnpacked<T_Val, T_Dep>& a, const VlUnpacked<T_Val, T_Dep>& b) {
+        for (int i = 0; i < T_Dep; ++i) {
+            // Recursive 'neq', in case T_Val is also a VlUnpacked<_, _>
+            if (neq(a.m_storage[i], b.m_storage[i])) return true;
+        }
+        return false;
+    }
+
+    template <typename T_Other>  //
+    inline static bool neq(const T_Other& a, const T_Other& b) {
+        // Base case (T_Other is not VlUnpacked<_, _>), fall back on !=
+        return a != b;
+    }
 };
 
 template <class T_Value, std::size_t T_Depth>

src/V3Sched.cpp

@@ -325,6 +325,11 @@ class SenExprBuilder final {
             return {nullptr, false};  // We already warn for this in V3LinkResolve
         case VEdgeType::ET_CHANGED:
         case VEdgeType::ET_HYBRID:  //
+            if (VN_IS(senp->dtypep(), UnpackArrayDType)) {
+                AstCMethodHard* const resultp = new AstCMethodHard{flp, currp(), "neq", prevp()};
+                resultp->dtypeSetBit();
+                return {resultp, true};
+            }
             return {new AstNeq(flp, currp(), prevp()), true};
         case VEdgeType::ET_BOTHEDGE:  //
             return {lsb(new AstXor{flp, currp(), prevp()}), false};

test_regress/t/t_comb_loop_through_unpacked_array.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Geza Lore. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt_all => 1);
+
+compile(
+  verilator_flags2 => ["-Wno-UNOPTFLAT"]
+  );
+
+ok(1);
+1;

test_regress/t/t_comb_loop_through_unpacked_array.v

@@ -0,0 +1,30 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// Copyright 2022 by Geza Lore. This program is free software; you can
+// redistribute it and/or modify it under the terms of either the GNU
+// Lesser General Public License Version 3 or the Perl Artistic License
+// Version 2.0.
+// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+module top(
+  input wire a,
+  input wire b,
+  output wire o
+);
+
+  logic [255:0] array [1:0];
+  logic [255:0] tmp [1:0];
+
+  // Nonsensical, but needs to compile. (In some real designs we can end up
+  // with combinational loops via unpacked arrays)
+  always_comb begin
+    tmp[0] = array[a];
+  end
+
+  always_comb begin
+    array[b] = tmp[0];
+  end
+
+  assign o = array[0][0];
+
+endmodule