diff --git a/include/verilated_types.h b/include/verilated_types.h index 47cd12d9b..bb2ba2186 100644 --- a/include/verilated_types.h +++ b/include/verilated_types.h @@ -923,12 +923,9 @@ template struct VlUnpacked final { T_Value& operator[](size_t index) { return m_storage[index]; } const T_Value& operator[](size_t index) const { return m_storage[index]; } - bool operator!=(const VlUnpacked& that) const { - for (int i = 0; i < T_Depth; ++i) { - if (m_storage[i] != that.m_storage[i]) return true; - } - return false; - } + // *this != that, which might be used for change detection/trigger computation, but avoid + // operator overloading in VlUnpacked for safety in other contexts. + inline bool neq(const VlUnpacked& that) const { return neq(*this, that); } // Dumping. Verilog: str = $sformatf("%p", assoc) std::string to_string() const { @@ -940,6 +937,22 @@ template struct VlUnpacked final { } return out + "} "; } + +private: + template + static bool neq(const VlUnpacked& a, const VlUnpacked& b) { + for (int i = 0; i < T_Dep; ++i) { + // Recursive 'neq', in case T_Val is also a VlUnpacked<_, _> + if (neq(a.m_storage[i], b.m_storage[i])) return true; + } + return false; + } + + template // + inline static bool neq(const T_Other& a, const T_Other& b) { + // Base case (T_Other is not VlUnpacked<_, _>), fall back on != + return a != b; + } }; template diff --git a/src/V3Sched.cpp b/src/V3Sched.cpp index c5e44719b..a65cdd008 100644 --- a/src/V3Sched.cpp +++ b/src/V3Sched.cpp @@ -325,6 +325,11 @@ class SenExprBuilder final { return {nullptr, false}; // We already warn for this in V3LinkResolve case VEdgeType::ET_CHANGED: case VEdgeType::ET_HYBRID: // + if (VN_IS(senp->dtypep(), UnpackArrayDType)) { + AstCMethodHard* const resultp = new AstCMethodHard{flp, currp(), "neq", prevp()}; + resultp->dtypeSetBit(); + return {resultp, true}; + } return {new AstNeq(flp, currp(), prevp()), true}; case VEdgeType::ET_BOTHEDGE: // return {lsb(new AstXor{flp, currp(), prevp()}), false}; diff --git a/test_regress/t/t_comb_loop_through_unpacked_array.pl b/test_regress/t/t_comb_loop_through_unpacked_array.pl new file mode 100755 index 000000000..c7f63144c --- /dev/null +++ b/test_regress/t/t_comb_loop_through_unpacked_array.pl @@ -0,0 +1,18 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2022 by Geza Lore. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(vlt_all => 1); + +compile( + verilator_flags2 => ["-Wno-UNOPTFLAT"] + ); + +ok(1); +1; diff --git a/test_regress/t/t_comb_loop_through_unpacked_array.v b/test_regress/t/t_comb_loop_through_unpacked_array.v new file mode 100644 index 000000000..1e2d26052 --- /dev/null +++ b/test_regress/t/t_comb_loop_through_unpacked_array.v @@ -0,0 +1,30 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// Copyright 2022 by Geza Lore. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +module top( + input wire a, + input wire b, + output wire o +); + + logic [255:0] array [1:0]; + logic [255:0] tmp [1:0]; + + // Nonsensical, but needs to compile. (In some real designs we can end up + // with combinational loops via unpacked arrays) + always_comb begin + tmp[0] = array[a]; + end + + always_comb begin + array[b] = tmp[0]; + end + + assign o = array[0][0]; + +endmodule