diff --git a/test_regress/t/t_concat_large.v b/test_regress/t/t_concat_large.v index ee6d315f9..3e4c37caf 100644 --- a/test_regress/t/t_concat_large.v +++ b/test_regress/t/t_concat_large.v @@ -6,15 +6,15 @@ module t; - reg [32767:0] a; + reg [32767:0] a; - initial begin - a = {32768{1'b1}}; - if (a[32000] != 1'b1) $stop; - a = '0; - if (a[32000] != 1'b0) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + a = {32768{1'b1}}; + if (a[32000] != 1'b1) $stop; + a = '0; + if (a[32000] != 1'b0) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_concat_large_bad.out b/test_regress/t/t_concat_large_bad.out index 2b458b997..b38ad127c 100644 --- a/test_regress/t/t_concat_large_bad.out +++ b/test_regress/t/t_concat_large_bad.out @@ -1,11 +1,11 @@ -%Warning-WIDTHCONCAT: t/t_concat_large_bad.v:10:23: Replication of more that --replication-limit 8192 is suspect: 32768 +%Warning-WIDTHCONCAT: t/t_concat_large_bad.v:10:22: Replication of more that --replication-limit 8192 is suspect: 32768 : ... note: In instance 't' - 10 | wire [32767:0] b = '0; - | ^~ + 10 | wire [32767:0] b = '0; + | ^~ ... For warning description see https://verilator.org/warn/WIDTHCONCAT?v=latest ... Use "/* verilator lint_off WIDTHCONCAT */" and lint_on around source to disable this message. -%Warning-WIDTHCONCAT: t/t_concat_large_bad.v:9:29: Replication of more that --replication-limit 8192 is suspect: 32768 +%Warning-WIDTHCONCAT: t/t_concat_large_bad.v:9:28: Replication of more that --replication-limit 8192 is suspect: 32768 : ... note: In instance 't' - 9 | wire [32767:0] a = {32768{1'b1}}; - | ^ + 9 | wire [32767:0] a = {32768{1'b1}}; + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_concat_large_bad.v b/test_regress/t/t_concat_large_bad.v index e97257ce0..5920c79fc 100644 --- a/test_regress/t/t_concat_large_bad.v +++ b/test_regress/t/t_concat_large_bad.v @@ -6,11 +6,11 @@ module t; - wire [32767:0] a = {32768{1'b1}}; - wire [32767:0] b = '0; + wire [32767:0] a = {32768{1'b1}}; + wire [32767:0] b = '0; - initial begin - $stop; - end + initial begin + $stop; + end endmodule diff --git a/test_regress/t/t_reloop_inlined.v b/test_regress/t/t_reloop_inlined.v index 2f838d88b..e2cc17cc5 100644 --- a/test_regress/t/t_reloop_inlined.v +++ b/test_regress/t/t_reloop_inlined.v @@ -10,12 +10,12 @@ module t; always #5 clk1 = ~clk1; always #10 clk2 = ~clk2; - int iarray [63:0]; - int oarray1 [63:0]; - int oarray2 [63:0]; + int iarray[63:0]; + int oarray1[63:0]; + int oarray2[63:0]; initial begin - for (int i = 0; i < 64 ; i = i + 1) begin + for (int i = 0; i < 64; i = i + 1) begin iarray[i] = i; end @@ -30,13 +30,13 @@ module t; end always @(posedge clk1) begin - for (int i = 0; i < 64 ; i = i + 1) begin + for (int i = 0; i < 64; i = i + 1) begin oarray1[i] = iarray[i]; end end always @(posedge clk2) begin - for (int i = 0; i < 64 ; i = i + 1) begin - oarray2[i] =iarray[i]; + for (int i = 0; i < 64; i = i + 1) begin + oarray2[i] = iarray[i]; end end