Resolve data types of method calls without parenthesis (#6457)

Signed-off-by: Artur Bieniek <abieniek@internships.antmicro.com>
This commit is contained in:
Artur Bieniek 2025-09-19 13:43:22 +02:00 committed by GitHub
parent 0391f113b0
commit c1ac2a79db
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
3 changed files with 40 additions and 4 deletions

View File

@ -3313,10 +3313,13 @@ class WidthVisitor final : public VNVisitor {
VL_DO_DANGLING(pushDeletep(nodep), nodep);
return true;
}
if (VN_IS(foundp, NodeFTask)) {
nodep->replaceWith(new AstMethodCall{nodep->fileline(),
nodep->fromp()->unlinkFrBack(),
nodep->name(), nullptr});
if (AstNodeFTask* ftaskp = VN_CAST(foundp, NodeFTask)) {
AstMethodCall* newp = new AstMethodCall{
nodep->fileline(), nodep->fromp()->unlinkFrBack(), nodep->name(), nullptr};
newp->taskp(ftaskp);
newp->dtypep(ftaskp->dtypep());
newp->classOrPackagep(classp);
nodep->replaceWith(newp);
VL_DO_DANGLING(pushDeletep(nodep), nodep);
return true;
}

View File

@ -0,0 +1,16 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2025 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt')
test.compile()
test.passes()

View File

@ -0,0 +1,17 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2025 by Antmicro.
// SPDX-License-Identifier: CC0-1.0
class c;
function f();
endfunction
endclass
module t;
c cinst;
initial begin
cinst = new();
if(cinst.f) begin end
end
endmodule