Resolve data types of method calls without parenthesis (#6457)
Signed-off-by: Artur Bieniek <abieniek@internships.antmicro.com>
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@ -3313,10 +3313,13 @@ class WidthVisitor final : public VNVisitor {
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VL_DO_DANGLING(pushDeletep(nodep), nodep);
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return true;
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}
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if (VN_IS(foundp, NodeFTask)) {
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nodep->replaceWith(new AstMethodCall{nodep->fileline(),
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nodep->fromp()->unlinkFrBack(),
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nodep->name(), nullptr});
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if (AstNodeFTask* ftaskp = VN_CAST(foundp, NodeFTask)) {
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AstMethodCall* newp = new AstMethodCall{
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nodep->fileline(), nodep->fromp()->unlinkFrBack(), nodep->name(), nullptr};
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newp->taskp(ftaskp);
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newp->dtypep(ftaskp->dtypep());
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newp->classOrPackagep(classp);
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nodep->replaceWith(newp);
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VL_DO_DANGLING(pushDeletep(nodep), nodep);
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return true;
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}
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@ -0,0 +1,16 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2025 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('vlt')
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test.compile()
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test.passes()
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@ -0,0 +1,17 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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class c;
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function f();
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endfunction
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endclass
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module t;
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c cinst;
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initial begin
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cinst = new();
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if(cinst.f) begin end
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end
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endmodule
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