diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index a8a3691ec..194d4d9fe 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -3313,10 +3313,13 @@ class WidthVisitor final : public VNVisitor {
                     VL_DO_DANGLING(pushDeletep(nodep), nodep);
                     return true;
                 }
-                if (VN_IS(foundp, NodeFTask)) {
-                    nodep->replaceWith(new AstMethodCall{nodep->fileline(),
-                                                         nodep->fromp()->unlinkFrBack(),
-                                                         nodep->name(), nullptr});
+                if (AstNodeFTask* ftaskp = VN_CAST(foundp, NodeFTask)) {
+                    AstMethodCall* newp = new AstMethodCall{
+                        nodep->fileline(), nodep->fromp()->unlinkFrBack(), nodep->name(), nullptr};
+                    newp->taskp(ftaskp);
+                    newp->dtypep(ftaskp->dtypep());
+                    newp->classOrPackagep(classp);
+                    nodep->replaceWith(newp);
                     VL_DO_DANGLING(pushDeletep(nodep), nodep);
                     return true;
                 }
diff --git a/test_regress/t/t_func_ref_noparen.py b/test_regress/t/t_func_ref_noparen.py
new file mode 100755
index 000000000..319c0ff4a
--- /dev/null
+++ b/test_regress/t/t_func_ref_noparen.py
@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+
+test.compile()
+
+test.passes()
diff --git a/test_regress/t/t_func_ref_noparen.v b/test_regress/t/t_func_ref_noparen.v
new file mode 100644
index 000000000..75ab8e934
--- /dev/null
+++ b/test_regress/t/t_func_ref_noparen.v
@@ -0,0 +1,17 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Antmicro.
+// SPDX-License-Identifier: CC0-1.0
+
+class c;
+   function f();
+   endfunction
+endclass
+module t;
+   c cinst;
+   initial begin
+      cinst = new();
+      if(cinst.f) begin end
+   end
+endmodule