Fix associative array default type resolution
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7f871467bf
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c15489b711
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@ -5008,7 +5008,10 @@ class WidthVisitor final : public VNVisitor {
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}
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}
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void patternAssoc(AstPattern* nodep, AstAssocArrayDType* arrayDtp, AstPatMember* defaultp) {
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void patternAssoc(AstPattern* nodep, AstAssocArrayDType* arrayDtp, AstPatMember* defaultp) {
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AstNode* defaultValuep = nullptr;
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AstNode* defaultValuep = nullptr;
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if (defaultp) defaultValuep = defaultp->lhssp()->unlinkFrBack();
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if (defaultp) {
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defaultp->dtypep(arrayDtp->subDTypep());
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defaultValuep = patternMemberValueIterate(defaultp);
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}
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AstNodeExpr* newp = new AstConsAssoc{nodep->fileline(), defaultValuep};
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AstNodeExpr* newp = new AstConsAssoc{nodep->fileline(), defaultValuep};
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newp->dtypeFrom(arrayDtp);
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newp->dtypeFrom(arrayDtp);
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for (AstPatMember* patp = VN_AS(nodep->itemsp(), PatMember); patp;
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for (AstPatMember* patp = VN_AS(nodep->itemsp(), PatMember); patp;
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@ -5037,7 +5040,10 @@ class WidthVisitor final : public VNVisitor {
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void patternWildcard(AstPattern* nodep, AstWildcardArrayDType* arrayDtp,
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void patternWildcard(AstPattern* nodep, AstWildcardArrayDType* arrayDtp,
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AstPatMember* defaultp) {
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AstPatMember* defaultp) {
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AstNode* defaultValuep = nullptr;
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AstNode* defaultValuep = nullptr;
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if (defaultp) defaultValuep = defaultp->lhssp()->unlinkFrBack();
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if (defaultp) {
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defaultp->dtypep(arrayDtp->subDTypep());
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defaultValuep = patternMemberValueIterate(defaultp);
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}
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AstNode* newp = new AstConsWildcard{nodep->fileline(), defaultValuep};
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AstNode* newp = new AstConsWildcard{nodep->fileline(), defaultValuep};
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newp->dtypeFrom(arrayDtp);
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newp->dtypeFrom(arrayDtp);
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for (AstPatMember* patp = VN_AS(nodep->itemsp(), PatMember); patp;
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for (AstPatMember* patp = VN_AS(nodep->itemsp(), PatMember); patp;
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@ -0,0 +1,16 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2025 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('linter')
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test.lint()
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test.passes()
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@ -0,0 +1,20 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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class param_comp #(
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type T = bit
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);
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static function int get_type();
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endfunction
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endclass
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class test;
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virtual function void check_phase();
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int m_param_comp_bit_expect_wrapper[string] = '{default: param_comp#(bit)::get_type()};
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endfunction
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endclass
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endmodule
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