From c15489b7113578742538e301a4a0f7fe204c41ab Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Wed, 17 Sep 2025 23:39:47 -0400 Subject: [PATCH] Fix associative array default type resolution --- src/V3Width.cpp | 10 ++++++++-- test_regress/t/t_assoc_default_func.py | 16 ++++++++++++++++ test_regress/t/t_assoc_default_func.v | 20 ++++++++++++++++++++ 3 files changed, 44 insertions(+), 2 deletions(-) create mode 100755 test_regress/t/t_assoc_default_func.py create mode 100644 test_regress/t/t_assoc_default_func.v diff --git a/src/V3Width.cpp b/src/V3Width.cpp index c4de5b60c..c99024b8c 100644 --- a/src/V3Width.cpp +++ b/src/V3Width.cpp @@ -5008,7 +5008,10 @@ class WidthVisitor final : public VNVisitor { } void patternAssoc(AstPattern* nodep, AstAssocArrayDType* arrayDtp, AstPatMember* defaultp) { AstNode* defaultValuep = nullptr; - if (defaultp) defaultValuep = defaultp->lhssp()->unlinkFrBack(); + if (defaultp) { + defaultp->dtypep(arrayDtp->subDTypep()); + defaultValuep = patternMemberValueIterate(defaultp); + } AstNodeExpr* newp = new AstConsAssoc{nodep->fileline(), defaultValuep}; newp->dtypeFrom(arrayDtp); for (AstPatMember* patp = VN_AS(nodep->itemsp(), PatMember); patp; @@ -5037,7 +5040,10 @@ class WidthVisitor final : public VNVisitor { void patternWildcard(AstPattern* nodep, AstWildcardArrayDType* arrayDtp, AstPatMember* defaultp) { AstNode* defaultValuep = nullptr; - if (defaultp) defaultValuep = defaultp->lhssp()->unlinkFrBack(); + if (defaultp) { + defaultp->dtypep(arrayDtp->subDTypep()); + defaultValuep = patternMemberValueIterate(defaultp); + } AstNode* newp = new AstConsWildcard{nodep->fileline(), defaultValuep}; newp->dtypeFrom(arrayDtp); for (AstPatMember* patp = VN_AS(nodep->itemsp(), PatMember); patp; diff --git a/test_regress/t/t_assoc_default_func.py b/test_regress/t/t_assoc_default_func.py new file mode 100755 index 000000000..cca4c9e73 --- /dev/null +++ b/test_regress/t/t_assoc_default_func.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2025 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_assoc_default_func.v b/test_regress/t/t_assoc_default_func.v new file mode 100644 index 000000000..e4a3be8f8 --- /dev/null +++ b/test_regress/t/t_assoc_default_func.v @@ -0,0 +1,20 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2025 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t; + class param_comp #( + type T = bit + ); + static function int get_type(); + endfunction + endclass + + class test; + virtual function void check_phase(); + int m_param_comp_bit_expect_wrapper[string] = '{default: param_comp#(bit)::get_type()}; + endfunction + endclass +endmodule