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https://github.com/verilator/verilator.git
synced 2026-10-02 16:13:34 +02:00
Set status of finished process immediately (#8503)
Signed-off-by: Ryszard Rozak <[email protected]>
This commit is contained in:
@@ -545,10 +545,7 @@ class TransformForksVisitor final : public VNVisitor {
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// Replace the body of the begin with a call to the newly created function
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nodep->addStmtsp(callp->makeStmt());
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// Propagate if needs process
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if (nodep->needProcess()) {
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newfuncp->setNeedProcess();
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newfuncp->addStmtsp(new AstCStmt{flp, "vlProcess->state(VlProcess::FINISHED);"});
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}
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if (nodep->needProcess()) newfuncp->setNeedProcess();
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remapLocals(newfuncp, callp);
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}
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void visit(AstCAwait* nodep) override {
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@@ -1463,6 +1463,10 @@ class TimingControlVisitor final : public VNVisitor {
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// Name the begin (later the name will be used for a new function)
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itemp->name(nodep->name() + "__" + std::to_string(idx++));
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if (itemp->needProcess()) {
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itemp->addStmtsp(
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new AstCStmt{itemp->fileline(), "vlProcess->state(VlProcess::FINISHED);"});
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}
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}
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if (!nodep->joinType().joinNone()) makeForkJoin(nodep);
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}
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+18
@@ -0,0 +1,18 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of either the GNU Lesser General Public License Version 3
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# or the Perl Artistic License Version 2.0.
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# SPDX-FileCopyrightText: 2026 Wilson Snyder
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.compile(verilator_flags2=['--binary'])
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test.execute()
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test.passes()
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@@ -0,0 +1,24 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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module t;
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process proc;
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initial begin
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fork
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begin
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proc = process::self();
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#1;
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end
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#10;
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join_any
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if (proc.status() != process::FINISHED) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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