Commentary

Changes

@@ -5,12 +5,16 @@ indicates the contributor was also the author of the fix; Thanks!
 
 * Verilator 3.800***
 
+Application visible changes:
+
 **   SystemPerl is no longer required for tracing.
      Applications must use VerilatedVcdC class in place of SpTraceVcdC.
 
 **   SystemVerilog 1800-2009 is now the default language.
      Thus "global" etc are now keywords.  See the --language option.
 
+New features:
+
 **   Support SystemVerilog types "byte", "chandle", "int", "longint",
      "shortint", "time", "var" and "void" in variables and functions.
 
@@ -35,7 +39,10 @@ indicates the contributor was also the author of the fix; Thanks!
 
 ***  Support 1800-2009 define defaults and `undefineall.
 
-***  Add VARHIDDEN warning when signal name hides module name.
+***  Add -CFLAGS, -LDFLAGS, <file>.a, <file>.o, and <file>.so options.
+
+***  Speed compiles by avoiding including the STL iostream header.
+     Application programs may need to include it themselves to avoid errors.
 
 ***  Add experimental clock domain crossing checks.
 
@@ -43,10 +50,7 @@ indicates the contributor was also the author of the fix; Thanks!
 
 ***  Add experimental config files to filter warnings outside of the source.
 
-***  Add -CFLAGS, -LDFLAGS, <file>.a, <file>.o, and <file>.so options.
+***  Add VARHIDDEN warning when signal name hides module name.
-
-***  Speed compiles by avoiding including the STL iostream header.
-     Application programs may need to include it themselves to avoid errors.
 
 **** Support optional cell parenthesis, bug179. [by Byron Bradley]
 
@@ -60,11 +64,11 @@ indicates the contributor was also the author of the fix; Thanks!
 
 **** Add -Wno-MODDUP option to allow duplicate modules.
 
-**** Fix creating implicit variables for expressions, bug196. [Byron Bradley]
+Bug fixes:
 
-**** Fix duplicate implicit variables under generates, bug201. [Byron Bradley]
+**** Fix implicit variable issues, bug196, bug201. [Byron Bradley]
 
-**** Fix for variable typing, bug205.  [by Byron Bradley]
+**** Fix 'for' variable typing, bug205.  [by Byron Bradley]
 
 **** Fix tracing with --pins-bv 1, bug195.  [Michael S]
 

bin/verilator

@@ -159,7 +159,7 @@ Verilator - Convert Verilog code to C++/SystemC
     verilator --cc [options] [top_level.v] [opt_c_files.cpp/c/cc/a/o/so]
     verilator --sc [options] [top_level.v] [opt_c_files.cpp/c/cc/a/o/so]
     verilator --sp [options] [top_level.v] [opt_c_files.cpp/c/cc/a/o/so]
-    verilator --lint-only ...
+    verilator --lint-only    [top_level.v]...
 
 =head1 DESCRIPTION
 
@@ -184,6 +184,7 @@ The resulting executable will perform the actual simulation.
 
 To get started, jump down to "EXAMPLE C++ EXECUTION".
 
+
 =head1 ARGUMENT SUMMARY
 
 This is a short summary of the arguments to Verilator.  See the detailed
@@ -267,6 +268,7 @@ descriptions in the next sections for more information.
      -x-assign <mode>           Initially assign Xs to this value
      -y <dir>                   Directory to search for modules
 
+
 =head1 ARGUMENTS
 
 =over 4
@@ -838,6 +840,7 @@ compatibility.
 
 =back
 
+
 =head1 EXAMPLE C++ EXECUTION
 
 We'll compile this example into C++.
@@ -895,6 +898,7 @@ Really, you're better off writing a Makefile to do all this for you.  Then,
 when your source changes it will automatically run all of these steps.  See
 the test_c directory in the distribution for an example.
 
+
 =head1 EXAMPLE SYSTEMC EXECUTION
 
 This is an example similar to the above, but using SystemPerl.
@@ -965,6 +969,7 @@ Really, you're better off using a Makefile to do all this for you.  Then,
 when your source changes it will automatically run all of these steps.  See
 the test_sp directory in the distribution for an example.
 
+
 =head1 BENCHMARKING & OPTIMIZATION
 
 For best performance, run Verilator with the "-O3 -x-assign=fast
@@ -1019,6 +1024,7 @@ Verilog line numbers on which most of the time is being spent.
 When done, please let the author know the results.  I like to keep tabs on
 how Verilator compares, and may be able to suggest additional improvements.
 
+
 =head1 FILES
 
 All output files are placed in the output directory name specified with the
@@ -1068,6 +1074,7 @@ After running Make, the C++ compiler should produce the following:
     {prefix}__ALL.a			// Library of all Verilated objects
     {prefix}{misc}.o			// Intermediate objects
 
+
 =head1 ENVIRONMENT
 
 =over 4
@@ -1139,6 +1146,7 @@ Verilator was compiled).
 
 =back
 
+
 =head1 CONNECTING TO C++
 
 Verilator creates a .h and .cpp file for the top level module and all
@@ -1194,6 +1202,7 @@ You call the eval() method to evaluate the model.  When the simulation is
 complete call the final() method to wrap up any SystemVerilog final blocks,
 and complete any assertions.
 
+
 =head1 CONNECTING TO SYSTEMC
 
 Verilator will convert the top level module to a SC_MODULE.  This module
@@ -1209,6 +1218,7 @@ Lower modules are not pure SystemC code.  This is a feature, as using the
 SystemC pin interconnect scheme everywhere would reduce performance by an
 order of magnitude.
 
+
 =head1 DIRECT PROGRAMMING INTERFACE (DPI)
 
 Verilator supports SystemVerilog Direct Programming Interface import and
@@ -1302,6 +1312,7 @@ definitions.
 Instead of DPI exporting, there's also Verilator public functions, which
 are slightly faster, but less compatible.
 
+
 =head1 CROSS COMPILATION
 
 Verilator supports cross-compiling Verilated code.  This is generally used
@@ -1351,6 +1362,7 @@ For larger designs you'll want to automate this using makefiles, which pull
 the names of the .cpp files to compile in from the make variables generated
 in obj_dir/Vour_classes.mk.
 
+
 =head1 CONFIGURATION FILES
 
 In addition to the command line, warnings and other features may be
@@ -1395,6 +1407,7 @@ if ommitted).
 
 =back
 
+
 =head1 LANGUAGE STANDARD SUPPORT
 
 =head2 Verilog 2001 (IEEE 1364-2001) Support
@@ -1415,11 +1428,12 @@ Verilator currently has some support for SystemVerilog synthesis
 constructs. As SystemVerilog features enter common usage they are added;
 please file a bug if a feature you need is missing.
 
-Verilator supports ==? and !=? operators, $bits, $countones, $error,
+Verilator supports ==? and !=? operators, ++ and -- in some contexts,
-$fatal, $info, $isunknown, $onehot, $onehot0, $unit, $warning, always_comb,
+$bits, $countones, $error, $fatal, $info, $isunknown, $onehot, $onehot0,
-always_ff, always_latch, bit, byte, chandle, do-while, export, final,
+$unit, $warning, always_comb, always_ff, always_latch, bit, byte, chandle,
-import, int, logic, longint, package, program, shortint, time, var, void,
+do-while, enum, export, final, import, int, logic, longint, package,
-priority case/if, and unique case/if.
+program, shortint, time, typedef, var, void, priority case/if, and unique
+case/if.
 
 It also supports .name and .* interconnection.
 
@@ -1432,6 +1446,10 @@ Verilator implements a full SystemVerilog 2009 preprocessor, including
 function call-like preprocessor defines, default define arguments,
 `__FILE__, `__LINE__ and `undefineall.
 
+Verilator currently has some support for SystemVerilog 2009 synthesis
+constructs. As SystemVerilog features enter common usage they are added;
+please file a bug if a feature you need is missing.
+
 =head2 Sugar/PSL Support
 
 Most future work is being directed towards improving SystemVerilog
@@ -1475,6 +1493,7 @@ Verilator likewise also asserts any "unique" or "priority" SystemVerilog
 keywords on case statements.  However, "unique if" and "priority if" are
 currently simply ignored.
 
+
 =head1 LANGUAGE EXTENSIONS
 
 The following additional constructs are the extensions Verilator supports
@@ -1785,6 +1804,7 @@ Re-enable waveform tracing for all future signals that are declared.
 
 =back
 
+
 =head1 LANGUAGE LIMITATIONS
 
 There are some limitations and lack of features relative to a commercial
@@ -2079,6 +2099,7 @@ when displaying all times, model wide.
 
 =back
 
+
 =head1 ERRORS AND WARNINGS
 
 Warnings may be disabled in two ways.  First, when the warning is
@@ -2525,6 +2546,7 @@ program above:
 
 =back
 
+
 =head1 FAQ/FREQUENTLY ASKED QUESTIONS
 
 =over 4
@@ -2848,6 +2870,7 @@ SystemC module *may* be faster.)
 
 =back
 
+
 =head1 BUGS
 
 First, check the the coding limitations section.
@@ -2875,6 +2898,7 @@ L<http://www.veripool.org/verilator>.  The bug will become publicly
 visible; if this is unacceptable, mail the bug report to
 C<[email protected]>.
 
+
 =head1 HISTORY
 
 Verilator was conceived in 1994 by Paul Wasson at the Core Logic Group
@@ -2905,6 +2929,7 @@ Currently, various language features and performance enhancements are added
 as the need arises.  Verilator is now about 3x faster than in 2002, and is
 faster than many popular commercial simulators.
 
+
 =head1 CONTRIBUTORS
 
 Many people have provided ideas and other assistance with Verilator.
@@ -2942,6 +2967,7 @@ Xiaoliang.
 
 Thanks all.
 
+
 =head1 DISTRIBUTION
 
 The latest version is available from L<http://www.veripool.org/>.
@@ -2963,7 +2989,7 @@ Major concepts by Paul Wasson and Duane Galbi.
 
 L<verilator_profcfunc>, L<systemperl>, L<vcoverage>, L<make>
 
-And verilator_internals.txt in the distribution.
+And internals.txt in the distribution.
 
 =cut
 

readme.pod

@@ -45,10 +45,10 @@ Verilator is developed and has primary testing on:
 
     SuSE 11.1 AMD64 i686-linux-2.6.27, GCC 4.3.2
 
-Versions have also built on Redhat Linux, Windows under Cygwin, Macs, HPUX
+Versions have also built on Redhat Linux, Macs OS-X, HPUX and Solaris.  It
-and Solaris.  It should run with minor porting on any Linix-ish platform.
+should run with minor porting on any Linix-ish platform.  Verilator also
-Verilator also works on Windows under MinGW (gcc -mno-cygwin).  Verilated
+works on Windows under Cygwin, and Windows under MinGW (gcc -mno-cygwin).
-output (not Verilator itself) compiles under MSVC++ 2008.
+Verilated output (not Verilator itself) compiles under MSVC++ 2008.
 
 =head1 INSTALLATION
 
@@ -164,11 +164,11 @@ or reading verilator.txt in the same directory as this README.
 
 =head1 DIRECTORY STRUCTURE
 
-The directories in the kit de-taring are as follows:
+The directories in the kit after de-taring are as follows:
 
-    bin/verilator               => Compiler Wrapper invoked on user Verilog code
+    bin/verilator               => Compiler Wrapper invoked to Verilate code
     include/                    => Files that should be in your -I compiler path
-    include/verilated.cpp       => Global routines to link into your simulator
+    include/verilated*.cpp      => Global routines to link into your simulator
     include/verilated.h         => Global headers
     include/verilated.v         => Stub defines for linting
     include/verilated.mk        => Common makefile
@@ -184,4 +184,3 @@ The directories in the kit de-taring are as follows:
 =head1 LIMITATIONS
 
 See verilator.txt (or execute C<bin/verilator --help>) for limitations.
-