Tests: Untabify some tests.

test_regress/t/t_sys_delta_monitor.v

@@ -4,10 +4,10 @@
 // any use, without warranty, 2020 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 module t(/*AUTOARG*/);
-logic [31:0] tmp;
-logic [31:0] tmp2;
-logic [31:0] tmp3;
-initial begin
+   logic [31:0] tmp;
+   logic [31:0] tmp2;
+   logic [31:0] tmp3;
+   initial begin
       tmp = 0;
       $monitor("[%0t] monitor0 %h", $time, tmp);
       while (tmp < 32) begin
@@ -20,5 +20,5 @@ initial begin
       end
       $write("*-* All Finished *-*\n");
       $finish();
-end
+   end
 endmodule

test_regress/t/t_type_match.v

@@ -1,10 +1,5 @@
 // DESCRIPTION: Verilator: Verilog Test module
 //
-// This module takes a single clock input, and should either
-//      $write("*-* All Finished *-*\n");
-//      $finish;
-// on success, or $stop.
-//
 // issue #5125
 // type used for __Vtrigprevexpr signal do not match type used for i/o port
 //
@@ -44,40 +39,40 @@ endmodule
 
 
 module top (
-input  a,
-output d
-);
+            input a,
+            output d
+            );
 
-logic b;
-logic  c[1];
-assign c[0] = b;
+   logic          b;
+   logic          c[1];
+   assign c[0] = b;
 
-unit i_unit
-(
-.a (a),
-.b (b),
-.c (c),
-.d (d)
-);
+   unit i_unit
+     (
+      .a (a),
+      .b (b),
+      .c (c),
+      .d (d)
+      );
 
 endmodule
 
 
 module unit
-(
-input a,
-input c[1],
-output logic b,
-output logic d
-);
+  (
+   input        a,
+   input        c[1],
+   output logic b,
+   output logic d
+   );
 
-// no_inline required to prevent optimising away the interesing part ...
-/*verilator no_inline_module*/
+   // no_inline required to prevent optimising away the interesing part ...
+   /*verilator no_inline_module*/
 
-always_comb
-begin
+   always_comb
+     begin
         b = a;
         d = b && c[0];
-end
+     end
 
 endmodule