diff --git a/.devcontainer/devcontainer.json b/.devcontainer/devcontainer.json
index c2235983d..c0ab75ebf 100644
--- a/.devcontainer/devcontainer.json
+++ b/.devcontainer/devcontainer.json
@@ -1,7 +1,7 @@
 {
-	"name": "Verilator Build Environment",
+        "name": "Verilator Build Environment",
 
-	"build": {
+        "build": {
         "dockerfile": "../ci/docker/buildenv/Dockerfile"
     }
 
diff --git a/ci/ci-win-compile.ps1 b/ci/ci-win-compile.ps1
index d5a469fd4..1cc694248 100644
--- a/ci/ci-win-compile.ps1
+++ b/ci/ci-win-compile.ps1
@@ -11,14 +11,14 @@
 Set-PSDebug -Trace 1
 
 if (-Not (Test-Path $PWD/../.ccache/win_bison.exe)) {
-	git clone --depth 1 https://github.com/lexxmark/winflexbison
-	cd winflexbison
-	mkdir build
-	cd build
-	cmake .. --install-prefix $PWD/../../../.ccache
-	cmake --build . --config Release -j 3
-	cmake --install . --prefix $PWD/../../../.ccache
-	cd ../..
+    git clone --depth 1 https://github.com/lexxmark/winflexbison
+    cd winflexbison
+    mkdir build
+    cd build
+    cmake .. --install-prefix $PWD/../../../.ccache
+    cmake --build . --config Release -j 3
+    cmake --install . --prefix $PWD/../../../.ccache
+    cd ../..
 }
 
 mkdir build
diff --git a/test_regress/t/t_cxx_equal_to.v b/test_regress/t/t_cxx_equal_to.v
index e35c8d6d6..09dd11f82 100644
--- a/test_regress/t/t_cxx_equal_to.v
+++ b/test_regress/t/t_cxx_equal_to.v
@@ -38,7 +38,7 @@ module t;
   end
 
   Test test(.out(out), .in(in),
-	    .clk(clk), .rst(rst));
+            .clk(clk), .rst(rst));
 endmodule
 
 
diff --git a/test_regress/t/t_event_control_prev_name_collision.v b/test_regress/t/t_event_control_prev_name_collision.v
index 2b95b86c5..ef9a9c660 100644
--- a/test_regress/t/t_event_control_prev_name_collision.v
+++ b/test_regress/t/t_event_control_prev_name_collision.v
@@ -44,7 +44,7 @@ module Q(
 endmodule
 
 module Test(
-  input        	reset,
+  input         reset,
   output        valid
 );
   wire ready_e;
diff --git a/test_regress/t/t_lint_top_bad.v b/test_regress/t/t_lint_top_bad.v
index eb3ae9d37..22980818f 100644
--- a/test_regress/t/t_lint_top_bad.v
+++ b/test_regress/t/t_lint_top_bad.v
@@ -7,7 +7,7 @@
 module sub(input wire clk, cpu_reset);
    reg reset_r;
    always @(posedge clk) begin
-      reset_r <= cpu_reset;	 // The problematic one
+      reset_r <= cpu_reset;      // The problematic one
    end
 endmodule
 
diff --git a/test_regress/t/t_queue_unknown_sel.v b/test_regress/t/t_queue_unknown_sel.v
index a62e5f031..489c7bcee 100644
--- a/test_regress/t/t_queue_unknown_sel.v
+++ b/test_regress/t/t_queue_unknown_sel.v
@@ -16,21 +16,21 @@ package z_pkg;
    localparam int MASKW=DATAW/8;
    localparam int SIZEW=4;
    typedef enum   logic [OPCODEW-1:0] {
-				       A   = 3'h 0,
-				       B   = 3'h 1
-				       } a_op_t;
+                                       A   = 3'h 0,
+                                       B   = 3'h 1
+                                       } a_op_t;
    typedef enum   logic [OPCODEW-1:0] {
-				       C   = 3'h 0,
-				       D   = 3'h 1
-				       } b_op_t;
+                                       C   = 3'h 0,
+                                       D   = 3'h 1
+                                       } b_op_t;
    typedef enum   logic [OPCODEW-1:0] {
-				       E   = 3'h 0,
-				       F   = 3'h 1
-				       } c_op_t;
+                                       E   = 3'h 0,
+                                       F   = 3'h 1
+                                       } c_op_t;
    typedef enum   logic [OPCODEW-1:0] {
-				       G       = 3'h 0,
-				       H       = 3'h 1
-				       } d_op_t;
+                                       G       = 3'h 0,
+                                       H       = 3'h 1
+                                       } d_op_t;
    typedef logic [CIDW-1:0] cid_t;
    typedef logic [SIDW-1:0] sid_t;
    typedef logic [CTAGW-1:0] ctag_t;
@@ -40,17 +40,17 @@ package z_pkg;
    typedef logic [SIZEW-1:0]  size_t;
    typedef logic [DATAW-1:0]  data_t;
    typedef logic [MASKW-1:0]  mask_t;
-   typedef struct 	      packed {
+   typedef struct             packed {
       cid_t        cid;
       a_op_t       opcode;
       address_t    address;
    } x1_ch_t;
-   typedef struct 	      packed {
+   typedef struct             packed {
       cid_t        cid;
       b_op_t      opcode;
       address_t    address;
    } x2_ch_t;
-   typedef struct 	      packed {
+   typedef struct             packed {
       cid_t        cid;
       sid_t        sid;
       ctag_t       ctag;
@@ -59,61 +59,61 @@ package z_pkg;
       state_t   state2;
       state_t   state3;
       address_t    address;
-      logic 		      f4;
+      logic                   f4;
       size_t       size;
-      logic 		      f2;
+      logic                   f2;
    } x3_ch_t;
-   typedef struct 	      packed {
+   typedef struct             packed {
       cid_t        cid;
       sid_t        sid;
       ctag_t       ctag;
       stag_t       stag;
       d_op_t       opcode;
       state_t   state1;
-      logic 		      f4;
-      logic 		      f1;
+      logic                   f4;
+      logic                   f1;
       size_t       size;
-      logic 		      f3;
+      logic                   f3;
    } x4_ch_t;
-   typedef struct 	      packed {
+   typedef struct             packed {
       cid_t        cid;
       ctag_t       ctag;
       stag_t       stag;
       d_op_t       opcode;
-      logic 		      f1;
-      logic 		      f3;
+      logic                   f1;
+      logic                   f3;
    } x5_ch_t;
-   typedef struct 	      packed {
-      logic 		      last;
-      logic 		      corrupt;
+   typedef struct             packed {
+      logic                   last;
+      logic                   corrupt;
    } x6_ch_t;
-   typedef struct 	      packed {
+   typedef struct             packed {
       sid_t        sid;
       stag_t       stag;
    } x7_ch_t;
-   typedef enum 	      {
-			       CH_X1,
-			       CH_Y1,
-			       CH_Y2,
-			       CH_X2,
-			       CH_X3,
-			       CH_Y3,
-			       CH_X4,
-			       CH_X5,
-			       CH_X6,
-			       CH_X7
-			       } channel_t;
+   typedef enum               {
+                               CH_X1,
+                               CH_Y1,
+                               CH_Y2,
+                               CH_X2,
+                               CH_X3,
+                               CH_Y3,
+                               CH_X4,
+                               CH_X5,
+                               CH_X6,
+                               CH_X7
+                               } channel_t;
    parameter channel_t CH_ALL[CH_X7+1] = '{CH_X1, CH_Y1, CH_Y2, CH_X2, CH_X3, CH_Y3, CH_X4, CH_X5, CH_X6, CH_X7};
-   typedef enum 	      {
-			       TXN_0,
-			       TXN_1,
-			       TXN_2,
-			       TXN_3,
-			       TXN_4,
-			       TXN_5,
-			       TXN_6,
-			       TXN_7
-			       } txn_type_t;
+   typedef enum               {
+                               TXN_0,
+                               TXN_1,
+                               TXN_2,
+                               TXN_3,
+                               TXN_4,
+                               TXN_5,
+                               TXN_6,
+                               TXN_7
+                               } txn_type_t;
    function txn_type_t txn_type(bit [2:0] opcode, channel_t ch);
       case(opcode)
         3'd0: begin
@@ -219,47 +219,47 @@ interface z_if;
    function automatic logic x5_trig(); return x5_valid; endfunction
    function automatic logic x6_trig(); return x6_valid; endfunction
    modport sender (
-		   output x1_valid,
-		   output x1,
-		   input  x2_valid,
-		   input  x2,
-		   output x3_valid,
-		   output x3,
-		   input  x4_valid,
-		   input  x4,
-		   input  x5_valid,
-		   input  x5,
-		   input  x6_valid,
-		   input  x6,
-		   input  x6_data,
-		   output x7_valid,
-		   output x7,
-		   import x2_trig,
-		   import x4_trig,
-		   import x5_trig,
-		   import x6_trig
-		   );
+                   output x1_valid,
+                   output x1,
+                   input  x2_valid,
+                   input  x2,
+                   output x3_valid,
+                   output x3,
+                   input  x4_valid,
+                   input  x4,
+                   input  x5_valid,
+                   input  x5,
+                   input  x6_valid,
+                   input  x6,
+                   input  x6_data,
+                   output x7_valid,
+                   output x7,
+                   import x2_trig,
+                   import x4_trig,
+                   import x5_trig,
+                   import x6_trig
+                   );
    modport receiver (
-		     input  x1_valid,
-		     input  x1,
-		     output x2_valid,
-		     output x2,
-		     input  x3_valid,
-		     input  x3,
-		     output x4_valid,
-		     output x4,
-		     output x5_valid,
-		     output x5,
-		     output x6_valid,
-		     output x6,
-		     output x6_data,
-		     input  x7_valid,
-		     input  x7,
-		     import x2_trig,
-		     import x4_trig,
-		     import x5_trig,
-		     import x6_trig
-		     );
+                     input  x1_valid,
+                     input  x1,
+                     output x2_valid,
+                     output x2,
+                     input  x3_valid,
+                     input  x3,
+                     output x4_valid,
+                     output x4,
+                     output x5_valid,
+                     output x5,
+                     output x6_valid,
+                     output x6,
+                     output x6_data,
+                     input  x7_valid,
+                     input  x7,
+                     import x2_trig,
+                     import x4_trig,
+                     import x5_trig,
+                     import x6_trig
+                     );
 endinterface
 class z_txn_class;
    import z_pkg::*;
@@ -273,14 +273,14 @@ class z_txn_class;
    rand state_t   state1;
    rand state_t   state2;
    rand state_t   state3;
-   rand logic 		    f1;
-   rand logic 		    f2;
-   rand logic 		    f3;
-   rand logic 		    f4;
+   rand logic               f1;
+   rand logic               f2;
+   rand logic               f3;
+   rand logic               f4;
    data_t            data[];
    mask_t            mask[];
-   bit 			    corrupt[];
-   logic [2:0] 		    req_opcode;
+   bit                      corrupt[];
+   logic [2:0]              req_opcode;
 endclass
 module z_bfm_sender import z_pkg::*;
    (
@@ -294,93 +294,93 @@ module z_bfm_sender import z_pkg::*;
    z_txn_class z_txn[ch.num()];
    always @(posedge clk or negedge reset_l) begin
       if (!reset_l) begin
-	 z_if_sender.x1_valid <= '0;
-	 z_if_sender.x3_valid <= '0;
-	 z_if_sender.x7_valid <= '0;
+         z_if_sender.x1_valid <= '0;
+         z_if_sender.x3_valid <= '0;
+         z_if_sender.x7_valid <= '0;
       end
       else begin
-	 foreach (CH_ALL[i]) begin
-	    case(CH_ALL[i])
+         foreach (CH_ALL[i]) begin
+            case(CH_ALL[i])
               CH_X1: begin
-		 if (z_txn_qs[i].size() > 0) begin
-		    z_txn[i] = z_txn_qs[i].pop_front();
-		    z_if_sender.x1_valid     <= '1;
-		    z_if_sender.x1.cid       <= z_txn[i].cid;
-		    z_if_sender.x1.opcode    <= a_op_t'(z_txn[i].req_opcode);
-		    z_if_sender.x1.address   <= z_txn[i].address;
-		 end
-	      end
+                 if (z_txn_qs[i].size() > 0) begin
+                    z_txn[i] = z_txn_qs[i].pop_front();
+                    z_if_sender.x1_valid     <= '1;
+                    z_if_sender.x1.cid       <= z_txn[i].cid;
+                    z_if_sender.x1.opcode    <= a_op_t'(z_txn[i].req_opcode);
+                    z_if_sender.x1.address   <= z_txn[i].address;
+                 end
+              end
               CH_X3: begin
-		 if (z_txn_qs[i].size() > 0) begin
-		    z_txn[i] = z_txn_qs[i].pop_front();
-		    z_if_sender.x3_valid     <= '1;
-		    z_if_sender.x3.cid       <= z_txn[i].cid;
-		    z_if_sender.x3.sid       <= z_txn[i].sid;
-		    z_if_sender.x3.ctag      <= z_txn[i].ctag;
-		    z_if_sender.x3.stag      <= z_txn[i].stag;
-		    z_if_sender.x3.opcode    <= c_op_t'(z_txn[i].req_opcode);
-		    z_if_sender.x3.state2    <= z_txn[i].state2;
-		    z_if_sender.x3.state3    <= z_txn[i].state3;
-		    z_if_sender.x3.address   <= z_txn[i].address;
-		    z_if_sender.x3.f4       <= z_txn[i].f4;
-		    z_if_sender.x3.size      <= z_txn[i].size;
-		    z_if_sender.x3.f2     <= z_txn[i].f2;
-		 end
-	      end
+                 if (z_txn_qs[i].size() > 0) begin
+                    z_txn[i] = z_txn_qs[i].pop_front();
+                    z_if_sender.x3_valid     <= '1;
+                    z_if_sender.x3.cid       <= z_txn[i].cid;
+                    z_if_sender.x3.sid       <= z_txn[i].sid;
+                    z_if_sender.x3.ctag      <= z_txn[i].ctag;
+                    z_if_sender.x3.stag      <= z_txn[i].stag;
+                    z_if_sender.x3.opcode    <= c_op_t'(z_txn[i].req_opcode);
+                    z_if_sender.x3.state2    <= z_txn[i].state2;
+                    z_if_sender.x3.state3    <= z_txn[i].state3;
+                    z_if_sender.x3.address   <= z_txn[i].address;
+                    z_if_sender.x3.f4       <= z_txn[i].f4;
+                    z_if_sender.x3.size      <= z_txn[i].size;
+                    z_if_sender.x3.f2     <= z_txn[i].f2;
+                 end
+              end
               CH_X7: begin
-		 if (z_txn_qs[i].size() > 0) begin
-		    z_txn[i] = z_txn_qs[i].pop_front();
-		    z_if_sender.x7.sid       <= z_txn[i].sid;
-		    z_if_sender.x7.stag      <= z_txn[i].stag;
-		 end
-	      end
+                 if (z_txn_qs[i].size() > 0) begin
+                    z_txn[i] = z_txn_qs[i].pop_front();
+                    z_if_sender.x7.sid       <= z_txn[i].sid;
+                    z_if_sender.x7.stag      <= z_txn[i].stag;
+                 end
+              end
               CH_X2: begin
-		 if (z_if_sender.x2_trig()) begin
-		    z_txn[i] = new;
-		    z_txn[i].req_txn_type = txn_type(z_if_sender.x2.opcode, ch);
-		    z_txn[i].cid          = z_if_sender.x2.cid;
-		    z_txn[i].address      = z_if_sender.x2.address;
-		    z_txn_qs[i].push_back(z_txn[i]);
-		 end
-	      end
+                 if (z_if_sender.x2_trig()) begin
+                    z_txn[i] = new;
+                    z_txn[i].req_txn_type = txn_type(z_if_sender.x2.opcode, ch);
+                    z_txn[i].cid          = z_if_sender.x2.cid;
+                    z_txn[i].address      = z_if_sender.x2.address;
+                    z_txn_qs[i].push_back(z_txn[i]);
+                 end
+              end
               CH_X4: begin
-		 if (z_if_sender.x4_trig()) begin
-		    z_txn[i] = new;
-		    z_txn[i].req_txn_type = txn_type(z_if_sender.x4.opcode, ch);
-		    z_txn[i].cid          = z_if_sender.x4.cid;
-		    z_txn[i].sid          = z_if_sender.x4.sid;
-		    z_txn[i].ctag         = z_if_sender.x4.ctag;
-		    z_txn[i].stag         = z_if_sender.x4.stag;
-		    z_txn[i].state1       = z_if_sender.x4.state1;
-		    z_txn[i].f1       = z_if_sender.x4.f1;
-		    z_txn[i].f4          = z_if_sender.x4.f4;
-		    z_txn[i].size         = z_if_sender.x4.size;
-		    z_txn[i].f3      = z_if_sender.x4.f3;
-		    z_txn_qs[i].push_back(z_txn[i]);
-		 end
-	      end
+                 if (z_if_sender.x4_trig()) begin
+                    z_txn[i] = new;
+                    z_txn[i].req_txn_type = txn_type(z_if_sender.x4.opcode, ch);
+                    z_txn[i].cid          = z_if_sender.x4.cid;
+                    z_txn[i].sid          = z_if_sender.x4.sid;
+                    z_txn[i].ctag         = z_if_sender.x4.ctag;
+                    z_txn[i].stag         = z_if_sender.x4.stag;
+                    z_txn[i].state1       = z_if_sender.x4.state1;
+                    z_txn[i].f1       = z_if_sender.x4.f1;
+                    z_txn[i].f4          = z_if_sender.x4.f4;
+                    z_txn[i].size         = z_if_sender.x4.size;
+                    z_txn[i].f3      = z_if_sender.x4.f3;
+                    z_txn_qs[i].push_back(z_txn[i]);
+                 end
+              end
               CH_X5: begin
-		 if (z_if_sender.x5_trig()) begin
-		    z_txn[i] = new;
-		    z_txn[i].req_txn_type = txn_type(z_if_sender.x5.opcode, ch);
-		    z_txn[i].cid          = z_if_sender.x5.cid;
-		    z_txn[i].ctag         = z_if_sender.x5.ctag;
-		    z_txn[i].f1       = z_if_sender.x5.f1;
-		    z_txn_qs[i].push_back(z_txn[i]);
-		 end
+                 if (z_if_sender.x5_trig()) begin
+                    z_txn[i] = new;
+                    z_txn[i].req_txn_type = txn_type(z_if_sender.x5.opcode, ch);
+                    z_txn[i].cid          = z_if_sender.x5.cid;
+                    z_txn[i].ctag         = z_if_sender.x5.ctag;
+                    z_txn[i].f1       = z_if_sender.x5.f1;
+                    z_txn_qs[i].push_back(z_txn[i]);
+                 end
               end
               CH_X6: begin
-		 if (z_if_sender.x6_trig()) begin
-		    z_txn[i] = new;
-		    z_txn[i].data         = new[1];
-		    z_txn[i].corrupt      = new[1];
-		    z_txn[i].data[0]      = z_if_sender.x6_data;
-		    z_txn[i].corrupt[0]   = z_if_sender.x6.corrupt;
-		    z_txn_qs[i].push_back(z_txn[i]);
-		 end
-	      end
-	    endcase
-	 end
+                 if (z_if_sender.x6_trig()) begin
+                    z_txn[i] = new;
+                    z_txn[i].data         = new[1];
+                    z_txn[i].corrupt      = new[1];
+                    z_txn[i].data[0]      = z_if_sender.x6_data;
+                    z_txn[i].corrupt[0]   = z_if_sender.x6.corrupt;
+                    z_txn_qs[i].push_back(z_txn[i]);
+                 end
+              end
+            endcase
+         end
       end
    end
 endmodule
@@ -392,9 +392,9 @@ module test_core_wrapper
    mmio_z
    );
    z_bfm_sender mem_z_bfm( .z_if_sender(z),
-			   .*);
+                           .*);
    z_bfm_sender mmio_z_bfm( .z_if_sender(mmio_z),
-		   	    .*);
+                            .*);
 endmodule
 module t
   (
@@ -404,6 +404,6 @@ module t
    z_if         z(),
      mmio_z();
    test_core_wrapper tile( .z     (z.sender),
-			   .mmio_z(mmio_z.sender),
-			   .*);
+                           .mmio_z(mmio_z.sender),
+                           .*);
 endmodule
diff --git a/test_regress/t/t_randomize_method_with_scoping.v b/test_regress/t/t_randomize_method_with_scoping.v
index 6e61399f2..a40d5ae49 100644
--- a/test_regress/t/t_randomize_method_with_scoping.v
+++ b/test_regress/t/t_randomize_method_with_scoping.v
@@ -5,10 +5,10 @@
 // SPDX-License-Identifier: CC0-1.0
 
 class c1;
-	rand int c1_f;
+        rand int c1_f;
 endclass
 class c2;
-	rand int c2_f;
+        rand int c2_f;
 endclass
 localparam int PARAM = 42;
 class Cls;
diff --git a/test_regress/t/t_select_mul_extend.v b/test_regress/t/t_select_mul_extend.v
index 0803259b0..dc9d2a1d4 100644
--- a/test_regress/t/t_select_mul_extend.v
+++ b/test_regress/t/t_select_mul_extend.v
@@ -19,19 +19,19 @@ module t(/*AUTOARG*/
 
    /*AUTOWIRE*/
    // Beginning of automatic wires (for undeclared instantiated-module outputs)
-   wire [31:0]		out;			// From test of Test.v
+   wire [31:0]          out;                    // From test of Test.v
    // End of automatics
 
    Test test(/*AUTOINST*/
-	     // Outputs
-	     .out			(out[31:0]),
-	     // Inputs
-	     .clk			(clk),
-	     .in			(in[31:0]));
+             // Outputs
+             .out                       (out[31:0]),
+             // Inputs
+             .clk                       (clk),
+             .in                        (in[31:0]));
 
    Test2 test2(/*AUTOINST*/
-	       // Inputs
-	       .clk			(clk));
+               // Inputs
+               .clk                     (clk));
 
    // Aggregate outputs into a single result vector
    wire [63:0] result = {32'h0, out};
@@ -87,7 +87,7 @@ module Test(/*AUTOARG*/
          if (i == (cond ? (2-cnt)%8 : 0)) begin
             q[i] = 31'(in);
          end
-	 else begin
+         else begin
             q[i] = '0;
          end
       end
diff --git a/test_regress/t/t_static_function_in_class.v b/test_regress/t/t_static_function_in_class.v
index ab9a80288..10a0b6e73 100644
--- a/test_regress/t/t_static_function_in_class.v
+++ b/test_regress/t/t_static_function_in_class.v
@@ -8,8 +8,8 @@ class string_utils;
   typedef string array_of_string[];
 
   static function array_of_string split_by_dash(string s);
-    string 	  parts[$];
-    int 	  last_char_position = -1;
+    string        parts[$];
+    int           last_char_position = -1;
     for (int i = 0; i < s.len(); i++) begin
       if (i == s.len()-1) begin
         parts.push_back(s.substr(last_char_position+1, i));
diff --git a/test_regress/t/t_sys_delta_monitor.pl b/test_regress/t/t_sys_delta_monitor.pl
index 4d6f55483..b30043275 100755
--- a/test_regress/t/t_sys_delta_monitor.pl
+++ b/test_regress/t/t_sys_delta_monitor.pl
@@ -11,7 +11,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 scenarios(simulator => 1);
 
 compile(
-	verilator_flags2 => ["--exe --main --timing --timescale 1ns/1ns"],
+    verilator_flags2 => ["--exe --main --timing --timescale 1ns/1ns"],
     );
 
 execute(
diff --git a/test_regress/t/t_sys_delta_monitor.v b/test_regress/t/t_sys_delta_monitor.v
index 7cccf594c..69ef3982f 100644
--- a/test_regress/t/t_sys_delta_monitor.v
+++ b/test_regress/t/t_sys_delta_monitor.v
@@ -4,21 +4,21 @@
 // any use, without warranty, 2020 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 module t(/*AUTOARG*/);
-logic [31:0] tmp;
-logic [31:0] tmp2;
-logic [31:0] tmp3;
-initial begin
-    tmp = 0;
-    $monitor("[%0t] monitor0 %h", $time, tmp);
-    while (tmp < 32) begin
-        tmp = tmp + 1;
-        if ((tmp % 5) == 1) begin
+   logic [31:0] tmp;
+   logic [31:0] tmp2;
+   logic [31:0] tmp3;
+   initial begin
+      tmp = 0;
+      $monitor("[%0t] monitor0 %h", $time, tmp);
+      while (tmp < 32) begin
+         tmp = tmp + 1;
+         if ((tmp % 5) == 1) begin
             tmp = tmp + 2;
             tmp = tmp + 1;
-        end
-		#1;
-    end
-    $write("*-* All Finished *-*\n");
-    $finish();
-end
+         end
+         #1;
+      end
+      $write("*-* All Finished *-*\n");
+      $finish();
+   end
 endmodule
diff --git a/test_regress/t/t_sys_monitor.v b/test_regress/t/t_sys_monitor.v
index 57e8d6c28..a1619464a 100644
--- a/test_regress/t/t_sys_monitor.v
+++ b/test_regress/t/t_sys_monitor.v
@@ -38,7 +38,7 @@ module t(/*AUTOARG*/
          $monitoron;
       end
       else if (cyc == 30) begin
-      	 $monitoroff;  // To avoid inconsistent output between --vlt and --vltmt
+         $monitoroff;  // To avoid inconsistent output between --vlt and --vltmt
          $write("*-* All Finished *-*\n");
          $finish;
       end
diff --git a/test_regress/t/t_trace_complex.v b/test_regress/t/t_trace_complex.v
index 763aef06c..354f83f57 100644
--- a/test_regress/t/t_trace_complex.v
+++ b/test_regress/t/t_trace_complex.v
@@ -8,11 +8,11 @@ bit global_bit;
 
 module t (clk);
    input clk;
-   integer      cyc = 0;
+   integer cyc = 0;
 
    typedef struct packed {
-      bit       b1;
-      bit       b0;
+      bit         b1;
+      bit         b0;
    } strp_t;
 
    typedef struct packed {
@@ -20,7 +20,7 @@ module t (clk);
       strp_t    x0;
    } strp_strp_t;
 
-   typedef union packed {
+   typedef union  packed {
       strp_t    x1;
       strp_t    x0;
    } unip_strp_t;
@@ -30,7 +30,7 @@ module t (clk);
 
    typedef strp_t [4:3] arrp_strp_t;
 
-   typedef bit arru_t [2:1];
+   typedef bit       arru_t [2:1];
    typedef arru_t arru_arru_t [4:3];
    typedef arrp_t arru_arrp_t [4:3];
    typedef strp_t arru_strp_t [4:3];
@@ -46,35 +46,35 @@ module t (clk);
    arru_arrp_t  v_arru_arrp;
    arru_strp_t  v_arru_strp;
 
-   real         v_real;
-   real         v_arr_real [2];
-   string       v_string;
-   chandle	v_chandle;
+   real              v_real;
+   real              v_arr_real [2];
+   string            v_string;
+   chandle           v_chandle;
 
-   string       v_assoc[string];
+   string            v_assoc[string];
    initial v_assoc["key"] = "value";
 
-   typedef struct packed {
-      logic [31:0] data;
+   typedef struct    packed {
+      logic [31:0]   data;
    } str32_t;
    str32_t [1:0] v_str32x2;  // If no --trace-struct, this packed array is traced as 63:0
    initial v_str32x2[0] = 32'hff;
    initial v_str32x2[1] = 0;
 
-   typedef enum int { ZERO=0, ONE, TWO, THREE } enumed_t;
+   typedef enum      int { ZERO=0, ONE, TWO, THREE } enumed_t;
    enumed_t v_enumed;
    enumed_t v_enumed2;
-   typedef enum logic [2:0] { BZERO=0, BONE, BTWO, BTHREE } enumb_t;
+   typedef enum      logic [2:0] { BZERO=0, BONE, BTWO, BTHREE } enumb_t;
    enumb_t v_enumb;
-   typedef struct packed {
+   typedef struct    packed {
       enumb_t a;
       enumb_t b;
    } enumb2_str_t;
    enumb2_str_t v_enumb2_str;
 
-   logic [7:0] unpacked_array[-2:0];
+   logic [7:0]       unpacked_array[-2:0];
 
-   bit         LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND;
+   bit               LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND;
 
    p #(.PARAM(2)) p2 ();
    p #(.PARAM(3)) p3 ();
diff --git a/test_regress/t/t_trace_ub_misaligned_address.v b/test_regress/t/t_trace_ub_misaligned_address.v
index 379412d3a..40b351aa7 100644
--- a/test_regress/t/t_trace_ub_misaligned_address.v
+++ b/test_regress/t/t_trace_ub_misaligned_address.v
@@ -55,7 +55,7 @@ module t;
   end
 
   Test test(.out(out), .in(in),
-	    .clk(clk), .rst(rst));
+            .clk(clk), .rst(rst));
 endmodule
 
 
diff --git a/test_regress/t/t_type_match.v b/test_regress/t/t_type_match.v
index 7c91d571c..b6560e3ce 100644
--- a/test_regress/t/t_type_match.v
+++ b/test_regress/t/t_type_match.v
@@ -1,10 +1,5 @@
 // DESCRIPTION: Verilator: Verilog Test module
 //
-// This module takes a single clock input, and should either
-//      $write("*-* All Finished *-*\n");
-//      $finish;
-// on success, or $stop.
-//
 // issue #5125
 // type used for __Vtrigprevexpr signal do not match type used for i/o port
 //
@@ -26,58 +21,58 @@ module t (clk);
    initial cnt=1;
 
    always @ (posedge clk)
-   begin
-      cnt <= cnt + 1;
+     begin
+        cnt <= cnt + 1;
 
-      a <= cnt[0];
-      $display("%d %d %d", cnt, a, d);
-      if (d != a)
-	 $stop;
+        a <= cnt[0];
+        $display("%d %d %d", cnt, a, d);
+        if (d != a)
+          $stop;
 
-      if (cnt == 10) begin
-	 $write("*-* All Finished *-*\n");
-	 $finish;
-      end
-   end
+        if (cnt == 10) begin
+           $write("*-* All Finished *-*\n");
+           $finish;
+        end
+     end
 
 endmodule
 
 
 module top (
-input  a,
-output d
-);
+            input a,
+            output d
+            );
 
-logic b;
-logic  c[1];
-assign c[0] = b;
+   logic          b;
+   logic          c[1];
+   assign c[0] = b;
 
-unit i_unit
-(
-.a (a),
-.b (b),
-.c (c),
-.d (d)
-);
+   unit i_unit
+     (
+      .a (a),
+      .b (b),
+      .c (c),
+      .d (d)
+      );
 
 endmodule
 
 
 module unit
-(
-input a,
-input c[1],
-output logic b,
-output logic d
-);
+  (
+   input        a,
+   input        c[1],
+   output logic b,
+   output logic d
+   );
 
-// no_inline required to prevent optimising away the interesing part ...
-/*verilator no_inline_module*/
+   // no_inline required to prevent optimising away the interesing part ...
+   /*verilator no_inline_module*/
 
-always_comb
-begin
-  b = a;
-  d = b && c[0];
-end
+   always_comb
+     begin
+        b = a;
+        d = b && c[0];
+     end
 
 endmodule