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Tests: Untabify some tests.

This commit is contained in:
Wilson Snyder 2024-09-01 21:12:37 -04:00
parent c9970ff822
commit b698bfd850
15 changed files with 275 additions and 280 deletions
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5
test_regress/t/t_type_match.v
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@ -1,10 +1,5 @@
// DESCRIPTION: Verilator: Verilog Test module // DESCRIPTION: Verilator: Verilog Test module
// //
// This module takes a single clock input, and should either
// $write("*-* All Finished *-*\n");
// $finish;
// on success, or $stop.
//
// issue #5125 // issue #5125
// type used for __Vtrigprevexpr signal do not match type used for i/o port // type used for __Vtrigprevexpr signal do not match type used for i/o port
// //