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Fix capital S signed numbers.

This commit is contained in:
Wilson Snyder 2019-11-16 09:39:41 -05:00
parent 66727670f9
commit b1c14e485a
2 changed files with 6 additions and 6 deletions
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10
src/verilog.l
View File

@ -118,11 +118,11 @@ id [a-zA-Z_][a-zA-Z0-9_$]*
escid \\[^ \t\f\r\n]+
word [a-zA-Z0-9_]+
/* verilog numbers, constructed to not match the ' that begins a '( or '{ */
vnum1 [0-9]*?['']s?[bcodhBCODH][ \t\n]*[A-Fa-f0-9xXzZ_?]*
vnum2 [0-9]*?['']s?[01xXzZ]
vnum3 [0-9][_0-9]*[ \t\n]*['']s?[bcodhBCODH]?[ \t\n]*[A-Fa-f0-9xXzZ_?]+
vnum4 [0-9][_0-9]*[ \t\n]*['']s?[bcodhBCODH]
vnum5 [0-9][_0-9]*[ \t\n]*['']s
vnum1 [0-9]*?[''][sS]?[bcodhBCODH][ \t\n]*[A-Fa-f0-9xXzZ_?]*
vnum2 [0-9]*?[''][sS]?[01xXzZ]
vnum3 [0-9][_0-9]*[ \t\n]*[''][sS]?[bcodhBCODH]?[ \t\n]*[A-Fa-f0-9xXzZ_?]+
vnum4 [0-9][_0-9]*[ \t\n]*[''][sS]?[bcodhBCODH]
vnum5 [0-9][_0-9]*[ \t\n]*[''][sS]
vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
%%

2
test_regress/t/t_math_signed3.v
View File

@ -13,7 +13,7 @@ module t (/*AUTOARG*/);
wire [2:0] bug729_b = ~0;
// the $signed output is unsigned because the input is unsigned; the signedness does not change.
wire [0:0] bug729_yuu = $signed(2'b11) == 3'b111; //1'b0
wire [0:0] bug729_ysu = $signed(2'sb11) == 3'b111; //1'b0
wire [0:0] bug729_ysu = $signed(2'SB11) == 3'b111; //1'b0
wire [0:0] bug729_yus = $signed(2'b11) == 3'sb111; //1'b1
wire [0:0] bug729_yss = $signed(2'sb11) == 3'sb111; //1'b1
wire [0:0] bug729_zuu = 2'sb11 == 3'b111; //1'b0