From b1c14e485a9e9d12ec6b3504fd980c70b298053a Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sat, 16 Nov 2019 09:39:41 -0500 Subject: [PATCH] Fix capital S signed numbers. --- src/verilog.l | 10 +++++----- test_regress/t/t_math_signed3.v | 2 +- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/verilog.l b/src/verilog.l index 58860ed91..069553450 100644 --- a/src/verilog.l +++ b/src/verilog.l @@ -118,11 +118,11 @@ id [a-zA-Z_][a-zA-Z0-9_$]* escid \\[^ \t\f\r\n]+ word [a-zA-Z0-9_]+ /* verilog numbers, constructed to not match the ' that begins a '( or '{ */ -vnum1 [0-9]*?['']s?[bcodhBCODH][ \t\n]*[A-Fa-f0-9xXzZ_?]* -vnum2 [0-9]*?['']s?[01xXzZ] -vnum3 [0-9][_0-9]*[ \t\n]*['']s?[bcodhBCODH]?[ \t\n]*[A-Fa-f0-9xXzZ_?]+ -vnum4 [0-9][_0-9]*[ \t\n]*['']s?[bcodhBCODH] -vnum5 [0-9][_0-9]*[ \t\n]*['']s +vnum1 [0-9]*?[''][sS]?[bcodhBCODH][ \t\n]*[A-Fa-f0-9xXzZ_?]* +vnum2 [0-9]*?[''][sS]?[01xXzZ] +vnum3 [0-9][_0-9]*[ \t\n]*[''][sS]?[bcodhBCODH]?[ \t\n]*[A-Fa-f0-9xXzZ_?]+ +vnum4 [0-9][_0-9]*[ \t\n]*[''][sS]?[bcodhBCODH] +vnum5 [0-9][_0-9]*[ \t\n]*[''][sS] vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} %% diff --git a/test_regress/t/t_math_signed3.v b/test_regress/t/t_math_signed3.v index c932ac376..079dfca84 100644 --- a/test_regress/t/t_math_signed3.v +++ b/test_regress/t/t_math_signed3.v @@ -13,7 +13,7 @@ module t (/*AUTOARG*/); wire [2:0] bug729_b = ~0; // the $signed output is unsigned because the input is unsigned; the signedness does not change. wire [0:0] bug729_yuu = $signed(2'b11) == 3'b111; //1'b0 - wire [0:0] bug729_ysu = $signed(2'sb11) == 3'b111; //1'b0 + wire [0:0] bug729_ysu = $signed(2'SB11) == 3'b111; //1'b0 wire [0:0] bug729_yus = $signed(2'b11) == 3'sb111; //1'b1 wire [0:0] bug729_yss = $signed(2'sb11) == 3'sb111; //1'b1 wire [0:0] bug729_zuu = 2'sb11 == 3'b111; //1'b0