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Support {} in always sensitivity lists, bug745.

This commit is contained in:
Wilson Snyder 2014-04-21 19:39:28 -04:00
parent c41dfcf6ad
commit b0f4cf3c9c
3 changed files with 8 additions and 2 deletions
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2
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@ -21,6 +21,8 @@ indicates the contributor was also the author of the fix; Thanks!
**** Documentation fixes, bug723. [Glen Gibb] **** Documentation fixes, bug723. [Glen Gibb]
**** Support {} in always sensitivity lists, bug745. [Igor Lesik]
**** Fix tracing of package variables and real arrays. **** Fix tracing of package variables and real arrays.
**** Fix tracing of packed arrays without --trace-structs, bug742. [Jie Xu] **** Fix tracing of packed arrays without --trace-structs, bug742. [Jie Xu]

1
src/verilog.y
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@ -2085,6 +2085,7 @@ senitem<senitemp>: // IEEE: part of event_expression, non-'OR' ',' terms
| senitemVar { $$ = $1; } | senitemVar { $$ = $1; }
| '(' senitemVar ')' { $$ = $2; } | '(' senitemVar ')' { $$ = $2; }
//UNSUP expr { UNSUP } //UNSUP expr { UNSUP }
| '{' event_expression '}' { $$ = $2; }
//UNSUP expr yIFF expr { UNSUP } //UNSUP expr yIFF expr { UNSUP }
// Since expr is unsupported we allow and ignore constants (removed in V3Const) // Since expr is unsupported we allow and ignore constants (removed in V3Const)
| yaINTNUM { $$ = NULL; } | yaINTNUM { $$ = NULL; }

7
test_regress/t/t_alw_combdly.v
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@ -11,7 +11,7 @@ module t (/*AUTOARG*/
input clk; input clk;
integer cyc; initial cyc=1; integer cyc; initial cyc=1;
reg [31:0] a, b, c, d, e, f, g; reg [31:0] a, b, c, d, e, f, g, h;
always @ (*) begin // Test Verilog 2001 (*) always @ (*) begin // Test Verilog 2001 (*)
// verilator lint_off COMBDLY // verilator lint_off COMBDLY
@ -33,6 +33,9 @@ module t (/*AUTOARG*/
always @ (1'b0, CONSTANT, f) begin // not technically legal, see bug412 always @ (1'b0, CONSTANT, f) begin // not technically legal, see bug412
g = f; g = f;
end end
always @ ({CONSTANT, g}) begin // bug745
h = g;
end
//always @ ((posedge b) or (a or b)) begin // note both illegal //always @ ((posedge b) or (a or b)) begin // note both illegal
always @ (posedge clk) begin always @ (posedge clk) begin
@ -46,7 +49,7 @@ module t (/*AUTOARG*/
if (c != 32'hfeedface) $stop; if (c != 32'hfeedface) $stop;
end end
if (cyc==3) begin if (cyc==3) begin
if (g != 32'hfeedface) $stop; if (h != 32'hfeedface) $stop;
end end
if (cyc==7) begin if (cyc==7) begin
$write("*-* All Finished *-*\n"); $write("*-* All Finished *-*\n");