From b0f4cf3c9c3c349d590ef0128124a2ad80a3812d Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Mon, 21 Apr 2014 19:39:28 -0400
Subject: [PATCH] Support {} in always sensitivity lists, bug745.

---
 Changes                        | 2 ++
 src/verilog.y                  | 1 +
 test_regress/t/t_alw_combdly.v | 7 +++++--
 3 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/Changes b/Changes
index 0c3d0057f..bbb7df81f 100644
--- a/Changes
+++ b/Changes
@@ -21,6 +21,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 ****  Documentation fixes, bug723. [Glen Gibb]
 
+****  Support {} in always sensitivity lists, bug745. [Igor Lesik]
+
 ****  Fix tracing of package variables and real arrays.
 
 ****  Fix tracing of packed arrays without --trace-structs, bug742. [Jie Xu]
diff --git a/src/verilog.y b/src/verilog.y
index afba2e3bb..5e1cb0b4e 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -2085,6 +2085,7 @@ senitem<senitemp>:		// IEEE: part of event_expression, non-'OR' ',' terms
 	|	senitemVar				{ $$ = $1; }
 	|	'(' senitemVar ')'			{ $$ = $2; }
 	//UNSUP	expr					{ UNSUP }
+	|	'{' event_expression '}'		{ $$ = $2; }
 	//UNSUP	expr yIFF expr				{ UNSUP }
 	// Since expr is unsupported we allow and ignore constants (removed in V3Const)
 	|	yaINTNUM				{ $$ = NULL; }
diff --git a/test_regress/t/t_alw_combdly.v b/test_regress/t/t_alw_combdly.v
index 5e147eea6..b17127d6e 100644
--- a/test_regress/t/t_alw_combdly.v
+++ b/test_regress/t/t_alw_combdly.v
@@ -11,7 +11,7 @@ module t (/*AUTOARG*/
    input clk;
    integer cyc; initial cyc=1;
 
-   reg [31:0] a, b, c, d, e, f, g;
+   reg [31:0] a, b, c, d, e, f, g, h;
 
    always @ (*) begin   // Test Verilog 2001 (*)
       // verilator lint_off COMBDLY
@@ -33,6 +33,9 @@ module t (/*AUTOARG*/
    always @ (1'b0, CONSTANT, f) begin // not technically legal, see bug412
       g = f;
    end
+   always @ ({CONSTANT, g}) begin // bug745
+      h = g;
+   end
    //always @ ((posedge b) or (a or b)) begin // note both illegal
 
    always @ (posedge clk) begin
@@ -46,7 +49,7 @@ module t (/*AUTOARG*/
 	    if (c != 32'hfeedface) $stop;
 	 end
 	 if (cyc==3) begin
-	    if (g != 32'hfeedface) $stop;
+	    if (h != 32'hfeedface) $stop;
 	 end
 	 if (cyc==7) begin
 	    $write("*-* All Finished *-*\n");