luke
/
verilator
mirror of https://github.com/verilator/verilator.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Add parsing of Edge-control specifiers 

Signed-off-by: Krzysztof Sychla <ksychla@antmicro.com>
This commit is contained in:
Krzysztof Sychla 2025-03-31 14:38:43 +02:00
parent ec3ce82aa7
commit ae84cfc49a
2 changed files with 26 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
src/verilog.l
View File

@ -79,7 +79,7 @@ static double lexParseDouble(FileLine* fl, const char* textp, size_t length) {
%o 25000
%s V95 V01NC V01C V05 S05 S09 S12 S17 S23
%s ATTRMODE QQQ STRING TABLE
%s ATTRMODE QQQ STRING TABLE EDGEDESC
%s VA5 SAX VLT
%s SYSCHDR SYSCINT SYSCIMP SYSCIMPH SYSCCTOR SYSCDTOR
@ -328,6 +328,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
"default" { FL; return yDEFAULT; }
"defparam" { FL; return yDEFPARAM; }
"disable" { FL; return yDISABLE; }
"edge"/{ws}*"[" { FL; yy_push_state(EDGEDESC); return yEDGE; }
"edge" { FL; return yEDGE; }
"else" { FL; return yELSE; }
"end" { FL; return yEND; }
@ -1023,6 +1024,13 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
<TABLE><<EOF>> { FL; yylval.fl->v3error("EOF in 'table'");
yyleng = 0; yy_pop_state(); FL_BRK; yyterminate(); }
<EDGEDESC>{
01|10|[01][zZxX]|[zZxX][01] { FL; return yaEDGEDESC; }
}
<EDGEDESC>","|"[" { FL; return yytext[0]; }
<EDGEDESC>{ws} { FL_FWD; FL_BRK; } /* otherwise ignore white-space */
<EDGEDESC>"]" { FL; yy_pop_state(); return yytext[0]; }
/************************************************************************/
/* Preprocessor */
/* Common for all SYSC header states */

25
src/verilog.y
View File

@ -443,6 +443,8 @@ BISONPRE_VERSION(3.7,%define api.header.include {"V3ParseBison.h"})
// IEEE: string_literal
%token<strp> yaSTRING "STRING"
%token<strp> yaSTRING__IGNORE "STRING-ignored" // Used when expr:string not allowed
// IEEE: edge_descriptor
%token<nump> yaEDGEDESC "EDGE DESCRIPTOR"
%token<fl> yaTIMINGSPEC "TIMING SPEC ELEMENT"
@ -5797,14 +5799,21 @@ setuphold_timing_check<nodep>: // ==IEEE: $setuphold_timing_check
;
timing_check_event<nodeExprp>: // ==IEEE: $timing_check_event
terminal_identifier { $$ = $1; }
| yPOSEDGE terminal_identifier { $$ = $2; }
| yNEGEDGE terminal_identifier { $$ = $2; }
| yEDGE terminal_identifier { $$ = $2; }
| terminal_identifier yP_ANDANDAND expr { $$ = $1; }
| yPOSEDGE terminal_identifier yP_ANDANDAND expr { $$ = $2; }
| yNEGEDGE terminal_identifier yP_ANDANDAND expr { $$ = $2; }
| yEDGE terminal_identifier yP_ANDANDAND expr { $$ = $2; }
terminal_identifier { $$ = $1; }
| yPOSEDGE terminal_identifier { $$ = $2; }
| yNEGEDGE terminal_identifier { $$ = $2; }
| yEDGE terminal_identifier { $$ = $2; }
| yEDGE '[' edge_descriptor_list ']' terminal_identifier { $$ = $5; }
| terminal_identifier yP_ANDANDAND expr { $$ = $1; }
| yPOSEDGE terminal_identifier yP_ANDANDAND expr { $$ = $2; }
| yNEGEDGE terminal_identifier yP_ANDANDAND expr { $$ = $2; }
| yEDGE terminal_identifier yP_ANDANDAND expr { $$ = $2; }
| yEDGE '[' edge_descriptor_list ']' terminal_identifier yP_ANDANDAND expr { $$ = $5; }
;
edge_descriptor_list:
yaEDGEDESC { }
| edge_descriptor_list ',' yaEDGEDESC { }
;
timing_check_limit<nodeExprp>: