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Add correct definition of timing_check_limit 

Signed-off-by: Krzysztof Sychla <ksychla@antmicro.com>
This commit is contained in:
Krzysztof Sychla 2025-03-28 12:31:35 +01:00
parent 3e07b14ffc
commit ec3ce82aa7
2 changed files with 12 additions and 6 deletions
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17
src/verilog.y
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@ -5788,12 +5788,12 @@ system_timing_check<nodep>: // ==IEEE: system_timing_check
;
setuphold_timing_check<nodep>: // ==IEEE: $setuphold_timing_check
yD_SETUPHOLD '(' timing_check_event ',' timing_check_event ',' expr ',' expr ')' ';' { $$ = nullptr; }
| yD_SETUPHOLD '(' timing_check_event ',' timing_check_event ',' expr ',' expr ',' idAnyE ')' ';' { $$ = nullptr; }
| yD_SETUPHOLD '(' timing_check_event ',' timing_check_event ',' expr ',' expr ',' idAnyE ',' minTypMaxE ')' ';' { $$ = nullptr; }
| yD_SETUPHOLD '(' timing_check_event ',' timing_check_event ',' expr ',' expr ',' idAnyE ',' minTypMaxE ',' minTypMaxE ')' ';' { $$ = nullptr; }
| yD_SETUPHOLD '(' timing_check_event ',' timing_check_event ',' expr ',' expr ',' idAnyE ',' minTypMaxE ',' minTypMaxE ',' delayed_referenceE ')' ';' { $$ = new AstSetuphold{$1, $3, $5, $17}; }
| yD_SETUPHOLD '(' timing_check_event ',' timing_check_event ',' expr ',' expr ',' idAnyE ',' minTypMaxE ',' minTypMaxE ',' delayed_referenceE ',' delayed_referenceE ')' ';' { $$ = new AstSetuphold{$1, $3, $5, $17, $19}; }
yD_SETUPHOLD '(' timing_check_event ',' timing_check_event ',' timing_check_limit ',' timing_check_limit ')' ';' { $$ = nullptr; }
| yD_SETUPHOLD '(' timing_check_event ',' timing_check_event ',' timing_check_limit ',' timing_check_limit ',' idAnyE ')' ';' { $$ = nullptr; }
| yD_SETUPHOLD '(' timing_check_event ',' timing_check_event ',' timing_check_limit ',' timing_check_limit ',' idAnyE ',' minTypMaxE ')' ';' { $$ = nullptr; }
| yD_SETUPHOLD '(' timing_check_event ',' timing_check_event ',' timing_check_limit ',' timing_check_limit ',' idAnyE ',' minTypMaxE ',' minTypMaxE ')' ';' { $$ = nullptr; }
| yD_SETUPHOLD '(' timing_check_event ',' timing_check_event ',' timing_check_limit ',' timing_check_limit ',' idAnyE ',' minTypMaxE ',' minTypMaxE ',' delayed_referenceE ')' ';' { $$ = new AstSetuphold{$1, $3, $5, $17}; }
| yD_SETUPHOLD '(' timing_check_event ',' timing_check_event ',' timing_check_limit ',' timing_check_limit ',' idAnyE ',' minTypMaxE ',' minTypMaxE ',' delayed_referenceE ',' delayed_referenceE ')' ';' { $$ = new AstSetuphold{$1, $3, $5, $17, $19}; }
;
timing_check_event<nodeExprp>: // ==IEEE: $timing_check_event
@ -5807,6 +5807,11 @@ timing_check_event<nodeExprp>: // ==IEEE: $timing_check_event
| yEDGE terminal_identifier yP_ANDANDAND expr { $$ = $2; }
;
timing_check_limit<nodeExprp>:
expr { $$ = $1; }
| expr ':' expr ':' expr { $$ = $3; }
;
delayed_referenceE<nodeExprp>:
/*empty*/ { $$ = nullptr; }
| terminal_identifier { $$ = $1; }

1
test_regress/t/t_setuphold.v
View File

@ -32,6 +32,7 @@ module t (/*AUTOARG*/
$setuphold (posedge sh1, negedge sh3, 0, 0, notifier,,, sh2, sh4);
$setuphold (posedge clk, negedge d, 0, 0);
$setuphold (posedge clk, negedge d, (0:0:0), (0:0:0));
$setuphold (posedge clk, negedge d, 0:0:0, 0:0:0);
$setuphold (posedge clk, negedge d, 0, 0,,,,,);
$setuphold (posedge clk &&& sh1, BL_X[0], 0, 0, ,,,delayed_CLK, BL_0);
$setuphold (posedge clk &&& sh1, BL_1, 0, 0, ,,,delayed_CLK, BL_X2[4:1]);