Rewrite V3Width for better spec adherence when -Wno-WIDTH.

Changes

@@ -11,6 +11,10 @@ indicates the contributor was also the author of the fix; Thanks!
 
 **    Support streaming operators, bug649. [Glen Gibb]
 
+**    Fix expression problems with -Wno-WIDTH, bug729, bug736. [Clifford Wolf]
+      Where WIDTH warnings were ignored this might result in different
+      warning messages and results, though it should better match the spec.
+
 ***   Add --no-trace-params.
 
 ***   Add assertions on 'unique if', bug725. [Jeff Bush] 
@@ -31,8 +35,6 @@ indicates the contributor was also the author of the fix; Thanks!
 
 ****  Fix modport function import not-found error.
 
-****  Fix expression width problems with -Wno-WIDTH, bug729, bug736. [Clifford Wolf]
-
 ****  Fix power operator calculation, bug730, bug735. [Clifford Wolf]
 
 ****  Fix reporting struct members as reserved words, bug741. [Chris Randall]

src/V3Undriven.cpp

@@ -75,7 +75,7 @@ public:
 
 private:
     // METHODS
-    inline bool bitNumOk(int bit) const { return (bit*FLAGS_PER_BIT < (int)m_flags.size()); }
+    inline bool bitNumOk(int bit) const { return bit>=0 && (bit*FLAGS_PER_BIT < (int)m_flags.size()); }
     inline bool usedFlag(int bit) const { return m_usedWhole || m_flags[bit*FLAGS_PER_BIT + FLAG_USED]; }
     inline bool drivenFlag(int bit) const { return m_drivenWhole || m_flags[bit*FLAGS_PER_BIT + FLAG_DRIVEN]; }
     enum BitNamesWhich { BN_UNUSED, BN_UNDRIVEN, BN_BOTH };

test_regress/t/t_math_signed4.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;

test_regress/t/t_math_signed4.v

@@ -0,0 +1,113 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2014 by Wilson Snyder.
+
+`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); fail='1; end while(0)
+`define checkf(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); fail='1; end while(0)
+
+module t (/*AUTOARG*/);
+
+   bit fail;
+
+   localparam signed [3:0] bug737_p1 = 4'b1000;
+
+   wire [3:0] bug737_a = 4'b1010;
+   reg [5:0]  bug737_y;
+   reg signed [3:0] w4_s;
+   reg signed [4:0] w5_s;
+   reg [3:0] w4_u;
+   reg [4:0] w5_u;
+   real      r;
+   initial begin
+      // verilator lint_off WIDTH
+      bug737_y = bug737_a + (bug737_p1 + 4'sb0);
+      `checkh(bug737_y, 6'b010010);  //bug737
+
+      //         6u     +[6u]   4s  +[6s] 6s
+      bug737_y = 6'b001010 + (4'sb1000 + 6'sb0);
+      `checkh(bug737_y, 6'b010010);  //bug737, getx 000010
+
+      //         6u     +[6u]   4s  +[6s] 6s
+      bug737_y = 6'b001010 + (4'b1000 + 6'sb0);
+      `checkh(bug737_y, 6'b010010);  //ok
+
+      bug737_y = 6'b001010 + (6'sb111000 + 6'sb0);
+      `checkh(bug737_y, 6'b000010);  //ok
+
+      //                       v--- sign extends to 6-bits
+      bug737_y = 6'sb001010 + (4'sb1000 + 6'sb0);
+      `checkh(bug737_y, 6'b000010);  //ok
+
+      // From t_math_signed_3
+      w4_s = 4'sb1111 - 1'b1;
+      `checkh(w4_s,33'he);
+
+      w4_s = 4'sb1111 - 5'b00001;
+      `checkh(w4_s,33'he);
+
+      w4_s = 4'sb1111 - 1'sb1;
+      `checkh(w4_s,4'h0);
+      w5_s = 4'sb1111 - 1'sb1;
+      `checkh(w5_s,4'h0);
+
+      w4_s = 4'sb1111 - 4'sb1111;
+      `checkh(w4_s,4'h0);
+      w5_s = 4'sb1111 - 4'sb1111;
+      `checkh(w5_s,5'h0);
+
+      // The assign LHS being signed or unsigned does not matter per IEEE
+      // The upper add being signed DOES matter propagating to lower
+      w4_s = 4'sb1111 - (1'sb1 + 4'b0);   //1'sb1 not extended as unsigned add
+      `checkh(w4_s,4'he);
+      w4_s = 4'sb1111 - (1'sb1 + 4'sb0);  //1'sb1 does sign extend
+      `checkh(w4_s,4'h0);
+      w4_s = 4'b1111 - (1'sb1 + 4'sb0);  //1'sb1 does *NOT* sign extend
+      `checkh(w4_s,4'he);  // BUG, Verilator says 'h0
+
+      w5_u = 4'b1111 + 4'b0001;  // Extends to 5 bits due to LHS
+      `checkh(w5_u, 5'b10000);
+      w4_u = 4'b1111 + 4'b0001;  // Normal case
+      `checkh(w4_u, 4'b0000);
+
+      // Another example of promotion, the add is 4 bits wide
+      w4_u = 3'b111 + 3'b010;
+      `checkh(w4_u, 4'b1001);
+      //
+      w4_u = 3'sb111 * 3'sb001; // Signed output, LHS does not matter
+      `checkh(w4_u, 4'sb1111);
+      w4_s = 3'sb111 * 3'sb001; // Signed output
+      `checkh(w4_s, 4'sb1111);
+      w4_s = 3'b111 * 3'sb001;  // Unsigned output
+      `checkh(w4_s, 4'b0111);
+
+      // Conditionals get width from parent; are assignment-like
+      w4_u = 1'b0 ? 4'b0 : (2'b01+2'b11);
+      `checkh(w4_u, 4'b0100);
+      w4_u = 1'b0 ? 4'b0 : (6'b001000+6'b001000);
+      `checkh(w4_u, 4'b0000);
+
+      // If RHS is larger, that larger size is used
+      w4_u = 5'b10000 / 5'b00100;
+      `checkh(w4_u, 4'b0100);
+
+      // Reals do not propagate to children
+      r = 1.0 + ( 1 + (1 / 2));
+      `checkf(r, 2.0);
+
+      // Self determined sign extension
+      r = $itor(3'sb111);
+      `checkf(r, -1.0);
+
+      // If any part of case is real, all is real
+      case (22)
+	22.0: ;
+	22.1: $stop;
+	default: $stop;
+      endcase
+
+      if (fail) $stop;
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule