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Fix tristate duplicate __Vcellinp declaration
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+6
-5
@@ -266,10 +266,11 @@ AstAssignW* V3Inst::pinReconnectSimple(AstPin* pinp, AstCell* cellp, AstNodeModu
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// Done. Constant.
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} else {
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// Make a new temp wire
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//if (1||debug()>=9) { pinp->dumpTree(cout,"in_pin:"); }
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//if (1||debug()>=9) { pinp->dumpTree(cout,"-in_pin:"); }
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AstNode* pinexprp = pinp->exprp()->unlinkFrBack();
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string newvarname = ((pinVarp->isOutput() ? "__Vcellout__" : "__Vcellinp__")
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+cellp->name()+"__"+pinp->name());
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string newvarname = ((string)(pinVarp->isOutput() ? "__Vcellout" : "__Vcellinp")
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+(forTristate?"t":"") // Prevent name conflict if both tri & non-tri add signals
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+"__"+cellp->name()+"__"+pinp->name());
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AstVar* newvarp = new AstVar (pinVarp->fileline(), AstVarType::MODULETEMP, newvarname, pinVarp);
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// Important to add statement next to cell, in case there is a generate with same named cell
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cellp->addNextHere(newvarp);
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@@ -298,8 +299,8 @@ AstAssignW* V3Inst::pinReconnectSimple(AstPin* pinp, AstCell* cellp, AstNodeModu
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pinp->exprp(new AstVarRef (pinexprp->fileline(), newvarp, false));
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}
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if (assignp) cellp->addNextHere(assignp);
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//if (1||debug()) { pinp->dumpTree(cout," out:"); }
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//if (1||debug()) { assignp->dumpTree(cout," aout:"); }
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//if (debug()) { pinp->dumpTree(cout,"- out:"); }
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//if (debug()) { assignp->dumpTree(cout,"- aout:"); }
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}
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return assignp;
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}
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