From a948be184c0abf9d7edbe2004d1ddce1d514991c Mon Sep 17 00:00:00 2001
From: Justin Thiel <jthiel@hudson-trading.com>
Date: Tue, 26 Sep 2023 20:35:23 -0400
Subject: [PATCH] Tests: Add t_interface_localparam_unsup (#3857 partial)
 (#3858)

---
 docs/CONTRIBUTORS                             |  1 +
 .../t/t_interface_localparam_unsup.out        |  5 ++
 .../t/t_interface_localparam_unsup.pl         | 23 +++++++++
 test_regress/t/t_interface_localparam_unsup.v | 51 +++++++++++++++++++
 4 files changed, 80 insertions(+)
 create mode 100644 test_regress/t/t_interface_localparam_unsup.out
 create mode 100755 test_regress/t/t_interface_localparam_unsup.pl
 create mode 100644 test_regress/t/t_interface_localparam_unsup.v

diff --git a/docs/CONTRIBUTORS b/docs/CONTRIBUTORS
index b80f0bfc3..92c0ec46c 100644
--- a/docs/CONTRIBUTORS
+++ b/docs/CONTRIBUTORS
@@ -88,6 +88,7 @@ Josh Redford
 Julian Daube
 Julie Schwartz
 Julien Margetts
+Justin Thiel
 Kaleb Barrett
 Kamil Rakoczy
 Kanad Kanhere
diff --git a/test_regress/t/t_interface_localparam_unsup.out b/test_regress/t/t_interface_localparam_unsup.out
new file mode 100644
index 000000000..1ac204e0e
--- /dev/null
+++ b/test_regress/t/t_interface_localparam_unsup.out
@@ -0,0 +1,5 @@
+*-* All Finished *-*
+top.t.intf: symbolsPerBeat 16, symbolsPerBeatDivBy2 8, mismatch 0
+top.t.theCore.core_intf: symbolsPerBeat 64, symbolsPerBeatDivBy2 8, mismatch 1
+%Error: t/t_interface_localparam_unsup.v:23: Verilog $stop
+Aborting...
diff --git a/test_regress/t/t_interface_localparam_unsup.pl b/test_regress/t/t_interface_localparam_unsup.pl
new file mode 100755
index 000000000..fa08b1e33
--- /dev/null
+++ b/test_regress/t/t_interface_localparam_unsup.pl
@@ -0,0 +1,23 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2023 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    fails => $Self->{vlt_all},
+    expect_filename => $Self->{golden_filename},
+);
+
+ok(1);
+1;
diff --git a/test_regress/t/t_interface_localparam_unsup.v b/test_regress/t/t_interface_localparam_unsup.v
new file mode 100644
index 000000000..6deb411ae
--- /dev/null
+++ b/test_regress/t/t_interface_localparam_unsup.v
@@ -0,0 +1,51 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2023 by Justin Thiel.
+// SPDX-License-Identifier: CC0-1.0
+
+interface SimpleIntf
+#(
+   parameter int symbolsPerBeat = 16
+)
+();
+
+   // This value is calculated incorrectly for other instances of
+   // this interface when it is accessed via the HDL for any other
+   // instance of this interface
+   localparam int symbolsPerBeatDivBy2  = symbolsPerBeat/2;
+
+   localparam bit mismatch = (symbolsPerBeat != (2*symbolsPerBeatDivBy2) );
+
+   initial begin
+      $write("%m: symbolsPerBeat %0d, symbolsPerBeatDivBy2 %0d, mismatch %0d\n",
+             symbolsPerBeat, symbolsPerBeatDivBy2, mismatch);
+      if (mismatch) $stop;
+   end
+
+endinterface
+
+module Core(
+   SimpleIntf intf
+);
+
+   // NOTE: When this line is commented out the test will pass
+   localparam intf_symbolsPerBeatDivBy2 = intf.symbolsPerBeatDivBy2;
+
+   localparam int core_intf_symbolsPerBeat = 64;
+   SimpleIntf #(.symbolsPerBeat(core_intf_symbolsPerBeat)) core_intf ();
+
+endmodule
+
+module t();
+
+   SimpleIntf intf();
+
+   Core theCore (.intf);
+
+   initial begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule