diff --git a/Changes b/Changes index 2c3bca506..a27ded2de 100644 --- a/Changes +++ b/Changes @@ -11,6 +11,9 @@ contributors that suggested or implemented a given issue are shown in []. Thanks Verilator 5.045 devel ========================== +**Other:** + +* Remove `--xml-only`. Verilator 5.044 2026-01-01 diff --git a/bin/verilator b/bin/verilator index 4cd6e160c..626d1dda5 100755 --- a/bin/verilator +++ b/bin/verilator @@ -552,8 +552,6 @@ detailed descriptions of these arguments. --x-assign Assign non-initial Xs to this value --x-initial Assign initial Xs to this value --x-initial-edge Enable initial X->0 and X->1 edge triggers - --xml-only Create XML parser output - --xml-output XML output filename -y Directory to search for modules This is a short summary of the simulation runtime arguments, i.e. for the diff --git a/docs/guide/deprecations.rst b/docs/guide/deprecations.rst index e053befa1..edeb4201e 100644 --- a/docs/guide/deprecations.rst +++ b/docs/guide/deprecations.rst @@ -17,11 +17,6 @@ C++14 compiler support the Ubuntu LTS versions of GCC and clang use C++20 by default, estimated May 2028.) -XML output - Verilator currently supports XML parser output (enabled with - `--xml-only`). Support for `--xml-*` options will be deprecated no - sooner than January 2026. - `--make cmake` The `--make cmake` options is deprecated and will be removed no sooner than January 2026. Use `--make json` instead. Note that the CMake diff --git a/docs/guide/exe_verilator.rst b/docs/guide/exe_verilator.rst index b5e9a0edd..c5e2aeb6d 100644 --- a/docs/guide/exe_verilator.rst +++ b/docs/guide/exe_verilator.rst @@ -2198,23 +2198,16 @@ Summary: .. option:: --xml-only - Create XML output only, do not create any other output. + Removed in 5.046. - The XML format is intended to be used to leverage Verilator's parser and - elaboration to feed to other downstream tools. - - .. note:: - - This feature is deprecated in favor of :vlopt:`--json-only`. + Created XML output only, did not create any other output. .. option:: --xml-output - Specifies the filename for the XML output file. Using this option - automatically sets :vlopt:`--xml-only`. + Removed in 5.046. - .. note:: - - This feature is deprecated in favor of :vlopt:`--json-only`. + Specified the filename for the XML output file. Using this option + automatically set :vlopt:`--xml-only`. .. option:: -y diff --git a/docs/guide/files.rst b/docs/guide/files.rst index 6c4638e1d..d14e8b043 100644 --- a/docs/guide/files.rst +++ b/docs/guide/files.rst @@ -112,8 +112,6 @@ In specific debug and other modes, it also creates: - JSON tree information (from --json-only) * - *{prefix}*.tree.meta.json - JSON tree metadata (from --json-only) - * - *{prefix}*.xml - - XML tree information (from --xml) * - *{prefix}*\ __cdc.txt - Clock Domain Crossing checks (from --cdc) * - *{prefix}*\ __stats.txt diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt index 2c9f01fe8..a69bcd640 100644 --- a/src/CMakeLists.txt +++ b/src/CMakeLists.txt @@ -94,7 +94,6 @@ set(HEADERS V3EmitMk.h V3EmitMkJson.h V3EmitV.h - V3EmitXml.h V3Error.h V3ExecGraph.h V3Expand.h @@ -268,7 +267,6 @@ set(COMMON_SOURCES V3EmitMk.cpp V3EmitMkJson.cpp V3EmitV.cpp - V3EmitXml.cpp V3Error.cpp V3ExecGraph.cpp V3Expand.cpp diff --git a/src/Makefile_obj.in b/src/Makefile_obj.in index 20a6de776..9c8e51560 100644 --- a/src/Makefile_obj.in +++ b/src/Makefile_obj.in @@ -276,7 +276,6 @@ RAW_OBJS_PCH_ASTNOMT = \ V3EmitCSyms.o \ V3EmitMk.o \ V3EmitMkJson.o \ - V3EmitXml.o \ V3ExecGraph.o \ V3Expand.o \ V3Force.o \ diff --git a/src/V3AstAttr.h b/src/V3AstAttr.h index b73bb419c..0e511cb93 100644 --- a/src/V3AstAttr.h +++ b/src/V3AstAttr.h @@ -1019,10 +1019,6 @@ public: static const char* const names[] = {"", "input", "output", "inout", "ref", "const ref"}; return names[m_e]; } - string xmlKwd() const { // For historical reasons no "put" suffix - static const char* const names[] = {"", "in", "out", "inout", "ref", "const ref"}; - return names[m_e]; - } string prettyName() const { return verilogKwd(); } bool isAny() const { return m_e != NONE; } bool isInout() const { return m_e == INOUT; } diff --git a/src/V3EmitXml.cpp b/src/V3EmitXml.cpp deleted file mode 100644 index 1f4dd666f..000000000 --- a/src/V3EmitXml.cpp +++ /dev/null @@ -1,460 +0,0 @@ -// -*- mode: C++; c-file-style: "cc-mode" -*- -//************************************************************************* -// DESCRIPTION: Verilator: Emit Verilog from tree -// -// Code available from: https://verilator.org -// -//************************************************************************* -// -// Copyright 2004-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. -// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -// -//************************************************************************* - -#include "V3PchAstNoMT.h" // VL_MT_DISABLED_CODE_UNIT - -#include "V3EmitXml.h" - -#include "V3EmitCBase.h" - -#include -#include - -VL_DEFINE_DEBUG_FUNCTIONS; - -// ###################################################################### -// Emit statements and expressions - -class EmitXmlFileVisitor final : public VNVisitorConst { - // NODE STATE - // Entire netlist: - // AstNode::user1 -> uint64_t, number to connect crossrefs - const VNUser1InUse m_user1InUse; - - // MEMBERS - V3OutFile* const m_ofp; - uint64_t m_id = 0; - - // METHODS - - // Outfile methods - V3OutFile* ofp() const { return m_ofp; } - virtual void puts(const string& str) { ofp()->puts(str); } - virtual void putsNoTracking(const string& str) { ofp()->putsNoTracking(str); } - virtual void putsQuoted(const string& str) { - // Quote \ and " for use inside C programs - // Don't use to quote a filename for #include - #include doesn't \ escape. - // Duplicate in V3File - here so we can print to string - putsNoTracking("\""); - putsNoTracking(V3OutFormatter::quoteNameControls(str, V3OutFormatter::LA_XML)); - putsNoTracking("\""); - } - - // XML methods - void outputId(AstNode* nodep) { - if (!nodep->user1()) nodep->user1(++m_id); - puts("\"" + cvtToStr(nodep->user1()) + "\""); - } - void outputTag(AstNode* nodep, const string& tagin) { - string tag = tagin; - if (tag == "") tag = VString::downcase(nodep->typeName()); - puts("<" + tag); - puts(" " + nodep->fileline()->xmlDetailedLocation()); - if (VN_IS(nodep, NodeDType)) { - puts(" id="); - outputId(nodep); - } - if (nodep->name() != "") { - puts(" name="); - putsQuoted(nodep->prettyName()); - } - if (nodep->tag() != "") { - puts(" tag="); - putsQuoted(nodep->tag()); - } - if (const AstNodeDType* const dtp = VN_CAST(nodep, NodeDType)) { - if (dtp->subDTypep()) { - puts(" sub_dtype_id="); - outputId(dtp->subDTypep()->skipRefp()); - } - } else { - if (nodep->dtypep()) { - puts(" dtype_id="); - outputId(nodep->dtypep()->skipRefp()); - } - } - } - void outputChildrenEnd(AstNode* nodep, const string& tagin) { - string tag = tagin; - if (tag == "") tag = VString::downcase(nodep->typeName()); - if (nodep->op1p() || nodep->op2p() || nodep->op3p() || nodep->op4p()) { - puts(">\n"); - iterateChildrenConst(nodep); - puts("\n"); - } else { - puts("/>\n"); - } - } - - // VISITORS - void visit(AstAssignW* nodep) override { - outputTag(nodep, "contassign"); // IEEE: vpiContAssign - outputChildrenEnd(nodep, "contassign"); - } - void visit(AstCell* nodep) override { - outputTag(nodep, "instance"); // IEEE: vpiInstance - puts(" defName="); - putsQuoted(nodep->modName()); // IEEE vpiDefName - puts(" origName="); - putsQuoted(nodep->origName()); - outputChildrenEnd(nodep, "instance"); - } - void visit(AstNodeIf* nodep) override { - outputTag(nodep, "if"); - puts(">\n"); - iterateAndNextConstNull(nodep->condp()); - puts("\n"); - iterateAndNextConstNull(nodep->thensp()); - puts("\n"); - if (nodep->elsesp()) { - puts("\n"); - iterateAndNextConstNull(nodep->elsesp()); - puts("\n"); - } - puts("\n"); - } - void visit(AstLoop* nodep) override { - outputTag(nodep, "loop"); - puts(">\n"); - if (nodep->stmtsp()) { - puts("\n"); - iterateAndNextConstNull(nodep->stmtsp()); - puts("\n"); - } - if (nodep->contsp()) { - puts("\n"); - iterateAndNextConstNull(nodep->contsp()); - puts("\n"); - } - puts("\n"); - } - void visit(AstLoopTest* nodep) override { - outputTag(nodep, "looptest"); - puts(">\n"); - iterateAndNextConstNull(nodep->condp()); - puts("\n"); - } - void visit(AstNetlist* nodep) override { - puts("\n"); - iterateChildrenConst(nodep); - puts("\n"); - } - void visit(AstConstPool* nodep) override { - if (!v3Global.opt.xmlOnly()) { - puts("\n"); - iterateChildrenConst(nodep); - puts("\n"); - } - } - void visit(AstInitArray* nodep) override { - puts("\n"); - const auto& mapr = nodep->map(); - for (const auto& itr : mapr) { - puts("\n"); - iterateChildrenConst(itr.second); - puts("\n"); - } - puts("\n"); - } - void visit(AstNodeModule* nodep) override { - outputTag(nodep, ""); - puts(" origName="); - putsQuoted(nodep->origName()); - if (nodep->isTop()) puts(" topModule=\"1\""); // IEEE vpiTopModule - if (nodep->modPublic()) puts(" public=\"true\""); - outputChildrenEnd(nodep, ""); - } - void visit(AstVar* nodep) override { - const VVarType typ = nodep->varType(); - const string kw = nodep->verilogKwd(); - const string vt = nodep->dtypep() ? nodep->dtypep()->name() : ""; - outputTag(nodep, ""); - if (nodep->isIO()) { - puts(" dir="); - putsQuoted(kw); - if (nodep->pinNum() != 0) puts(" pinIndex=\"" + cvtToStr(nodep->pinNum()) + "\""); - puts(" vartype="); - putsQuoted(!vt.empty() ? vt : typ == VVarType::PORT ? "port" : "unknown"); - } else { - puts(" vartype="); - putsQuoted(!vt.empty() ? vt : kw); - } - puts(" origName="); - putsQuoted(nodep->origName()); - // Attributes - if (nodep->attrIsolateAssign()) puts(" isolate_assignments=\"true\""); - if (nodep->isLatched()) puts(" latched=\"true\""); - if (nodep->isSigPublic()) puts(" public=\"true\""); - if (nodep->isSigUserRdPublic()) puts(" public_flat_rd=\"true\""); - if (nodep->isSigUserRWPublic()) puts(" public_flat_rw=\"true\""); - if (nodep->isGParam()) { - puts(" param=\"true\""); - } else if (nodep->isParam()) { - puts(" localparam=\"true\""); - } - if (nodep->attrScBv()) puts(" sc_bv=\"true\""); - if (nodep->attrSFormat()) puts(" sformat=\"true\""); - outputChildrenEnd(nodep, ""); - } - void visit(AstPin* nodep) override { - // What we call a pin in verilator is a port in the IEEE spec. - outputTag(nodep, "port"); // IEEE: vpiPort - if (nodep->modVarp() && nodep->modVarp()->isIO()) { - puts(" direction=\"" + nodep->modVarp()->direction().xmlKwd() + "\""); - } - puts(" portIndex=\"" + cvtToStr(nodep->pinNum()) + "\""); // IEEE: vpiPortIndex - // Children includes vpiHighConn and vpiLowConn; we don't support port bits (yet?) - outputChildrenEnd(nodep, "port"); - } - void visit(AstSenItem* nodep) override { - outputTag(nodep, ""); - puts(" edgeType=\"" + cvtToStr(nodep->edgeType().ascii()) + "\""); // IEEE vpiTopModule - outputChildrenEnd(nodep, ""); - } - void visit(AstModportVarRef* nodep) override { - // Dump direction for Modport references - const string kw = nodep->direction().xmlKwd(); - outputTag(nodep, ""); - puts(" direction="); - putsQuoted(kw); - outputChildrenEnd(nodep, ""); - } - void visit(AstVarXRef* nodep) override { - outputTag(nodep, ""); - puts(" dotted="); - putsQuoted(nodep->dotted()); - outputChildrenEnd(nodep, ""); - } - void visit(AstNodeCCall* nodep) override { - outputTag(nodep, ""); - puts(" func="); - putsQuoted(nodep->funcp() ? nodep->funcp()->name() : nodep->name()); - outputChildrenEnd(nodep, ""); - } - void visit(AstSel* nodep) override { - outputTag(nodep, ""); - puts(" widthConst=\"" + cvtToStr(nodep->widthConst()) + "\""); - outputChildrenEnd(nodep, ""); - } - - // Data types - void visit(AstBasicDType* nodep) override { - outputTag(nodep, "basicdtype"); - if (nodep->isRanged()) { - puts(" left=\"" + cvtToStr(nodep->left()) + "\""); - puts(" right=\"" + cvtToStr(nodep->right()) + "\""); - } - if (nodep->isSigned()) puts(" signed=\"true\""); - puts("/>\n"); - } - void visit(AstIfaceRefDType* nodep) override { - string mpn; - outputTag(nodep, ""); - if (nodep->isModport()) mpn = nodep->modportName(); - puts(" modportname="); - putsQuoted(mpn); - outputChildrenEnd(nodep, ""); - } - void visit(AstDisplay* nodep) override { - outputTag(nodep, ""); - puts(" displaytype="); - putsQuoted(nodep->verilogKwd()); - outputChildrenEnd(nodep, ""); - } - void visit(AstElabDisplay* nodep) override { - outputTag(nodep, ""); - puts(" displaytype="); - putsQuoted(nodep->verilogKwd()); - outputChildrenEnd(nodep, ""); - } - void visit(AstExtend* nodep) override { - outputTag(nodep, ""); - puts(" width="); - putsQuoted(cvtToStr(nodep->width())); - puts(" widthminv="); - putsQuoted(cvtToStr(nodep->lhsp()->widthMinV())); - outputChildrenEnd(nodep, ""); - } - void visit(AstExtendS* nodep) override { - outputTag(nodep, ""); - puts(" width="); - putsQuoted(cvtToStr(nodep->width())); - puts(" widthminv="); - putsQuoted(cvtToStr(nodep->lhsp()->widthMinV())); - outputChildrenEnd(nodep, ""); - } - - // Default - void visit(AstNode* nodep) override { - outputTag(nodep, ""); - outputChildrenEnd(nodep, ""); - } - -public: - EmitXmlFileVisitor(AstNode* nodep, V3OutFile* ofp) - : m_ofp{ofp} { - iterateConst(nodep); - } - ~EmitXmlFileVisitor() override = default; -}; - -//###################################################################### -// List of module files xml visitor - -class ModuleFilesXmlVisitor final : public VNVisitorConst { - // MEMBERS - std::ostream& m_os; - std::set m_modulesCovered; - std::deque m_nodeModules; - - // METHODS - - // VISITORS - void visit(AstNetlist* nodep) override { - // Children are iterated backwards to ensure correct compilation order - iterateChildrenBackwardsConst(nodep); - } - void visit(AstNodeModule* nodep) override { - // Only list modules and interfaces - // Assumes modules and interfaces list is already sorted level wise - if (!nodep->dead() && (VN_IS(nodep, Module) || VN_IS(nodep, Iface)) - && m_modulesCovered.insert(nodep->fileline()->filename()).second) { - m_nodeModules.push_front(nodep->fileline()); - } - } - //----- - void visit(AstNode*) override { - // All modules are present at root so no need to iterate on children - } - -public: - // CONSTRUCTORS - ModuleFilesXmlVisitor(AstNetlist* nodep, std::ostream& os) - : m_os(os) { // Need () or GCC 4.8 false warning - // Operate on whole netlist - iterateConst(nodep); - // Xml output - m_os << "\n"; - for (const FileLine* ifp : m_nodeModules) { - m_os << "filenameLetters() << "\" filename=\"" - << ifp->filenameEsc() << "\" language=\"" << ifp->language().ascii() << "\"/>\n"; - } - m_os << "\n"; - } - ~ModuleFilesXmlVisitor() override = default; -}; - -//###################################################################### -// Hierarchy of Cells visitor - -class HierCellsXmlVisitor final : public VNVisitorConst { - // MEMBERS - std::ostream& m_os; - std::string m_hier; - bool m_hasChildren = false; - - // METHODS - - // VISITORS - void visit(AstConstPool*) override {} - - void visit(AstNodeModule* nodep) override { - if (nodep->level() >= 0 && nodep->isTop()) { - m_os << "\n"; - m_os << "fileline()->xmlDetailedLocation() // - << " name=\"" << nodep->prettyName() << "\"" << " submodname=\"" - << nodep->prettyName() << "\"" << " hier=\"" << nodep->prettyName() << "\""; - m_hier = nodep->prettyName() + "."; - m_hasChildren = false; - iterateChildrenConst(nodep); - if (m_hasChildren) { - m_os << "\n"; - } else { - m_os << "/>\n"; - } - m_os << "\n"; - } - } - void visit(AstCell* nodep) override { - if (nodep->modp() && nodep->modp()->dead()) return; - if (!m_hasChildren) m_os << ">\n"; - m_os << "fileline()->xmlDetailedLocation() << " name=\"" << nodep->name() - << "\"" << " submodname=\"" << nodep->modName() << "\"" << " hier=\"" - << m_hier + nodep->name() << "\""; - const std::string hier = m_hier; - m_hier += nodep->name() + "."; - m_hasChildren = false; - iterateChildrenConst(nodep->modp()); - if (m_hasChildren) { - m_os << "\n"; - } else { - m_os << "/>\n"; - } - m_hier = hier; - m_hasChildren = true; - } - void visit(AstGenBlock* nodep) override { - VL_RESTORER(m_hier); - if (nodep->name() != "") m_hier += nodep->name() + "."; - iterateChildrenConst(nodep); - } - void visit(AstBegin* nodep) override { - VL_RESTORER(m_hier); - if (nodep->name() != "") m_hier += nodep->name() + "."; - iterateChildrenConst(nodep); - } - //----- - void visit(AstNode* nodep) override { iterateChildrenConst(nodep); } - -public: - // CONSTRUCTORS - HierCellsXmlVisitor(AstNetlist* nodep, std::ostream& os) - : m_os(os) { // Need () or GCC 4.8 false warning - iterateConst(nodep); - } - ~HierCellsXmlVisitor() override = default; -}; - -//###################################################################### -// EmitXml class functions - -void V3EmitXml::emitxml() { - UINFO(2, __FUNCTION__ << ":"); - // All-in-one file - const string filename = (v3Global.opt.xmlOutput().empty() - ? v3Global.opt.makeDir() + "/" + v3Global.opt.prefix() + ".xml" - : v3Global.opt.xmlOutput()); - V3OutXmlFile of{filename}; - of.putsHeader(); - of.puts("\n"); - of.puts("\n"); - { - std::stringstream sstr; - FileLine::fileNameNumMapDumpXml(sstr); - of.puts(sstr.str()); - } - { - std::stringstream sstr; - const ModuleFilesXmlVisitor moduleFilesVisitor{v3Global.rootp(), sstr}; - const HierCellsXmlVisitor cellsVisitor{v3Global.rootp(), sstr}; - of.puts(sstr.str()); - } - const EmitXmlFileVisitor visitor{v3Global.rootp(), &of}; - of.puts("\n"); -} diff --git a/src/V3EmitXml.h b/src/V3EmitXml.h deleted file mode 100644 index c4caa9da0..000000000 --- a/src/V3EmitXml.h +++ /dev/null @@ -1,30 +0,0 @@ -// -*- mode: C++; c-file-style: "cc-mode" -*- -//************************************************************************* -// DESCRIPTION: Verilator: Emit XML code -// -// Code available from: https://verilator.org -// -//************************************************************************* -// -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. -// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -// -//************************************************************************* - -#ifndef VERILATOR_V3EMITXML_H_ -#define VERILATOR_V3EMITXML_H_ - -#include "config_build.h" -#include "verilatedos.h" - -//============================================================================ - -class V3EmitXml final { -public: - static void emitxml() VL_MT_DISABLED; -}; - -#endif // Guard diff --git a/src/V3FileLine.cpp b/src/V3FileLine.cpp index c202caf1a..b05f9f490 100644 --- a/src/V3FileLine.cpp +++ b/src/V3FileLine.cpp @@ -77,18 +77,6 @@ FileLineSingleton::fileNameIdx_t FileLineSingleton::nameToNumber(const string& f return idx; } -//! Support XML output -//! Experimental. Updated to also put out the language. -void FileLineSingleton::fileNameNumMapDumpXml(std::ostream& os) { - os << "\n"; - for (const auto& itr : m_namemap) { - os << "\n"; - } - os << "\n"; -} - void FileLineSingleton::fileNameNumMapDumpJson(std::ostream& os) { std::string sep = "\n "; os << "\"files\": {"; @@ -241,12 +229,6 @@ void FileLine::newContent() { m_contentLineno = 1; } -string FileLine::xmlDetailedLocation() const { - return "loc=\"" + cvtToStr(filenameLetters()) + "," + cvtToStr(firstLineno()) + "," - + cvtToStr(firstColumn()) + "," + cvtToStr(lastLineno()) + "," + cvtToStr(lastColumn()) - + "\""; -} - string FileLine::lineDirectiveStrg(int enterExit) const { return "`line "s + cvtToStr(lastLineno()) + " \"" + V3OutFormatter::quoteNameControls(filename()) + "\" " + cvtToStr(enterExit) + '\n'; diff --git a/src/V3FileLine.h b/src/V3FileLine.h index 486588e23..e2818690c 100644 --- a/src/V3FileLine.h +++ b/src/V3FileLine.h @@ -135,7 +135,6 @@ class FileLineSingleton final { m_names.clear(); m_languages.clear(); } - void fileNameNumMapDumpXml(std::ostream& os); void fileNameNumMapDumpJson(std::ostream& os); static string filenameLetters(fileNameIdx_t fileno) VL_PURE; @@ -368,7 +367,6 @@ public: string filebasenameNoExt() const; string firstColumnLetters() const VL_MT_SAFE; string profileFuncname() const; - string xmlDetailedLocation() const; string lineDirectiveStrg(int enterExit) const; // Turn on/off warning messages on this line. @@ -410,7 +408,6 @@ public: static string globalWarnOffParse(const string& msgs, bool turnOff) { return defaultFileLine().warnOffParse(msgs, turnOff); } - static void fileNameNumMapDumpXml(std::ostream& os) { singleton().fileNameNumMapDumpXml(os); } static void fileNameNumMapDumpJson(std::ostream& os) { singleton().fileNameNumMapDumpJson(os); } diff --git a/src/V3Options.cpp b/src/V3Options.cpp index ac6a3b7d5..13c46e813 100644 --- a/src/V3Options.cpp +++ b/src/V3Options.cpp @@ -948,14 +948,14 @@ void V3Options::notify() VL_MT_DISABLED { if (!outFormatOk() && v3Global.opt.main()) ccSet(); // --main implies --cc if not provided if (!outFormatOk() && !dpiHdrOnly() && !lintOnly() && !preprocOnly() && !serializeOnly()) { v3fatal("verilator: Need --binary, --cc, --sc, --dpi-hdr-only, --lint-only, " - "--xml-only, --json-only or --E option"); + "--json-only or --E option"); } if (m_build && (m_gmake || m_cmake || m_makeJson)) { cmdfl->v3error("--make cannot be used together with --build. Suggest see manual"); } - // m_build, m_preprocOnly, m_dpiHdrOnly, m_lintOnly, m_jsonOnly and m_xmlOnly are mutually + // m_build, m_preprocOnly, m_dpiHdrOnly, m_lintOnly, and m_jsonOnly are mutually // exclusive std::vector backendFlags; if (m_build) { @@ -967,7 +967,6 @@ void V3Options::notify() VL_MT_DISABLED { if (m_preprocOnly) backendFlags.push_back("-E"); if (m_dpiHdrOnly) backendFlags.push_back("--dpi-hdr-only"); if (m_lintOnly) backendFlags.push_back("--lint-only"); - if (m_xmlOnly) backendFlags.push_back("--xml-only"); if (m_jsonOnly) backendFlags.push_back("--json-only"); if (backendFlags.size() > 1) { std::string backendFlagsString = backendFlags.front(); @@ -1039,8 +1038,7 @@ void V3Options::notify() VL_MT_DISABLED { && !v3Global.opt.serializeOnly()); } - if (m_timing.isDefault() - && (v3Global.opt.jsonOnly() || v3Global.opt.lintOnly() || v3Global.opt.xmlOnly())) + if (m_timing.isDefault() && (v3Global.opt.jsonOnly() || v3Global.opt.lintOnly())) v3Global.opt.m_timing.setTrueOrFalse(true); if (trace()) { @@ -1944,17 +1942,6 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, } }); DECL_OPTION("-x-initial-edge", OnOff, &m_xInitialEdge); - DECL_OPTION("-xml-only", CbOnOff, [this, fl](bool flag) { - if (!m_xmlOnly && flag) - fl->v3warn(DEPRECATED, "Option --xml-only is deprecated, move to --json-only"); - m_xmlOnly = flag; - }); - DECL_OPTION("-xml-output", CbVal, [this, fl](const char* valp) { - if (!m_xmlOnly) - fl->v3warn(DEPRECATED, "Option --xml-only is deprecated, move to --json-only"); - m_xmlOutput = valp; - m_xmlOnly = true; - }); DECL_OPTION("-y", CbVal, [this, &optdir](const char* valp) { addIncDirUser(parseFileArg(optdir, string{valp})); diff --git a/src/V3Options.h b/src/V3Options.h index 6e75c373f..b329762e3 100644 --- a/src/V3Options.h +++ b/src/V3Options.h @@ -310,7 +310,6 @@ private: bool m_vpi = false; // main switch: --vpi bool m_waiverMultiline = false; // main switch: --waiver-multiline bool m_xInitialEdge = false; // main switch: --x-initial-edge - bool m_xmlOnly = false; // main switch: --xml-only int m_buildJobs = -1; // main switch: --build-jobs, -j int m_coverageExprMax = 32; // main switch: --coverage-expr-max @@ -380,7 +379,6 @@ private: string m_work = "work"; // main switch: --work {libname} string m_xAssign; // main switch: --x-assign string m_xInitial; // main switch: --x-initial - string m_xmlOutput; // main switch: --xml-output // Language is now held in FileLine, on a per-node basis. However we still // have a concept of the default language at a global level. @@ -589,8 +587,7 @@ public: bool vpi() const { return m_vpi; } bool waiverMultiline() const { return m_waiverMultiline; } bool xInitialEdge() const { return m_xInitialEdge; } - bool xmlOnly() const { return m_xmlOnly; } - bool serializeOnly() const { return m_xmlOnly || m_jsonOnly; } + bool serializeOnly() const { return m_jsonOnly; } bool topIfacesSupported() const { return lintOnly() && !hierarchical(); } int buildJobs() const VL_MT_SAFE { return m_buildJobs; } @@ -681,7 +678,6 @@ public: bool isWaiverOutput() const { return !m_waiverOutput.empty(); } string xAssign() const { return m_xAssign; } string xInitial() const { return m_xInitial; } - string xmlOutput() const { return m_xmlOutput; } const VStringSet& cppFiles() const { return m_cppFiles; } const VStringList& cFlags() const { return m_cFlags; } diff --git a/src/Verilator.cpp b/src/Verilator.cpp index 540f83d37..f895dffb8 100644 --- a/src/Verilator.cpp +++ b/src/Verilator.cpp @@ -51,7 +51,6 @@ #include "V3EmitMk.h" #include "V3EmitMkJson.h" #include "V3EmitV.h" -#include "V3EmitXml.h" #include "V3ExecGraph.h" #include "V3Expand.h" #include "V3File.h" @@ -139,7 +138,6 @@ static void emitJson() VL_MT_DISABLED { } static void emitSerialized() VL_MT_DISABLED { - if (v3Global.opt.xmlOnly()) V3EmitXml::emitxml(); if (v3Global.opt.jsonOnly()) emitJson(); } @@ -637,8 +635,7 @@ static void process() { emitSerialized(); } else if (v3Global.opt.debugCheck() && !v3Global.opt.lintOnly() && !v3Global.opt.dpiHdrOnly()) { - // Check XML/JSON when debugging to make sure no missing node types - V3EmitXml::emitxml(); + // Check JSON when debugging to make sure no missing node types emitJson(); } diff --git a/test_regress/t/t_constraint_xml.out b/test_regress/t/t_constraint_xml.out deleted file mode 100644 index f332f7ec3..000000000 --- a/test_regress/t/t_constraint_xml.out +++ /dev/null @@ -1,71 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/test_regress/t/t_constraint_xml.py b/test_regress/t/t_constraint_xml.py deleted file mode 100755 index f2bffa381..000000000 --- a/test_regress/t/t_constraint_xml.py +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt') - -out_filename = test.obj_dir + "/V" + test.name + ".xml" - -test.compile(verilator_flags2=['--no-std', '-Wno-DEPRECATED --xml-only', '-Wno-CONSTRAINTIGN'], - verilator_make_gmake=False, - make_top_shell=False, - make_main=False) - -test.files_identical(out_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_constraint_xml.v b/test_regress/t/t_constraint_xml.v deleted file mode 100644 index c455e919d..000000000 --- a/test_regress/t/t_constraint_xml.v +++ /dev/null @@ -1,76 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -class Packet; - rand int header; // 0..7 - rand int length; // 0..15 - rand int sublength; // 0..15 - rand bit if_4; - rand bit iff_5_6; - rand bit if_state_ok; - - rand int array[2]; // 2,4,6 - - string state; - - constraint empty {} - - constraint size { - header > 0 && header <= 7; - length <= 15; - length >= header; - length dist { [0:1], [2:5] :/ 2, 6 := 6, 7 := 10, 1}; - } - - constraint ifs { - if (header > 4) { - if_4 == '1; - } - if (header == 5 || header == 6) { - iff_5_6 == '1; - iff_5_6 == '1; - iff_5_6 == '1; - } else { - iff_5_6 == '0; - } - } - - constraint arr_uniq { - foreach (array[i]) { - array[i] inside {2, 4, 6}; - } - unique { array[0], array[1] }; - } - - constraint order { solve length before header; } - - constraint dis { - soft sublength; - disable soft sublength; - sublength <= length; - } - - constraint meth { - if (strings_equal(state, "ok")) - if_state_ok == '1; - } - - function bit strings_equal(string a, string b); - return a == b; - endfunction - -endclass - -module t; - - Packet p; - - initial begin - // Not testing use of constraints - $write("*-* All Finished *-*\n"); - $finish; - end -endmodule diff --git a/test_regress/t/t_dist_docs_options.py b/test_regress/t/t_dist_docs_options.py index e02e9603d..b8a8fa290 100755 --- a/test_regress/t/t_dist_docs_options.py +++ b/test_regress/t/t_dist_docs_options.py @@ -20,6 +20,8 @@ Doc_Waivers = [ '-order-clock-delay', # Deprecated '-pp-comments', # Deprecated '-prof-threads', # Deprecated + '-xml-only', # Removed + '-xml-output', # Removed ] Test_Waivers = [ diff --git a/test_regress/t/t_flag_noop_bad.out b/test_regress/t/t_flag_noop_bad.out index 44c3e6392..ddfc7d07c 100644 --- a/test_regress/t/t_flag_noop_bad.out +++ b/test_regress/t/t_flag_noop_bad.out @@ -1,2 +1,2 @@ -%Error: verilator: Need --binary, --cc, --sc, --dpi-hdr-only, --lint-only, --xml-only, --json-only or --E option +%Error: verilator: Need --binary, --cc, --sc, --dpi-hdr-only, --lint-only, --json-only or --E option ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. diff --git a/test_regress/t/t_flag_only_bad.out b/test_regress/t/t_flag_only_bad.out index 6fcbc3a92..5fef92226 100755 --- a/test_regress/t/t_flag_only_bad.out +++ b/test_regress/t/t_flag_only_bad.out @@ -1,3 +1,3 @@ -%Error: The following cannot be used together: --binary, -E, --dpi-hdr-only, --lint-only, --xml-only, --json-only. Suggest see manual +%Error: The following cannot be used together: --binary, -E, --dpi-hdr-only, --lint-only, --json-only. Suggest see manual ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_flag_only_bad.py b/test_regress/t/t_flag_only_bad.py index ebce0ba4b..e05e51d9a 100755 --- a/test_regress/t/t_flag_only_bad.py +++ b/test_regress/t/t_flag_only_bad.py @@ -13,7 +13,7 @@ test.scenarios('vlt') test.top_filename = "t/t_flag_main.v" test.lint( - verilator_flags2=["-Wno-DEPRECATED --binary -E --dpi-hdr-only --xml-only --json-only -Wall"], + verilator_flags2=["-Wno-DEPRECATED --binary -E --dpi-hdr-only --lint-only --json-only -Wall"], fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_flag_only_bad2.out b/test_regress/t/t_flag_only_bad2.out index ce4a5c345..d63f296b2 100755 --- a/test_regress/t/t_flag_only_bad2.out +++ b/test_regress/t/t_flag_only_bad2.out @@ -1,3 +1,3 @@ -%Error: The following cannot be used together: --build, -E, --dpi-hdr-only, --lint-only, --xml-only, --json-only. Suggest see manual +%Error: The following cannot be used together: --build, -E, --dpi-hdr-only, --lint-only, --json-only. Suggest see manual ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_flag_only_bad2.py b/test_regress/t/t_flag_only_bad2.py index 98e0fe1aa..1b2146a58 100755 --- a/test_regress/t/t_flag_only_bad2.py +++ b/test_regress/t/t_flag_only_bad2.py @@ -13,7 +13,7 @@ test.scenarios('vlt') test.top_filename = "t/t_flag_main.v" test.lint(verilator_flags2=[ - "-Wno-DEPRECATED --build -E -Wno-fatal --dpi-hdr-only --xml-only --json-only" + "-Wno-DEPRECATED --build -E -Wno-fatal --dpi-hdr-only --lint-only --json-only" ], fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_flag_only_bad3.out b/test_regress/t/t_flag_only_bad3.out index 604118317..d66aa2e93 100755 --- a/test_regress/t/t_flag_only_bad3.out +++ b/test_regress/t/t_flag_only_bad3.out @@ -1,3 +1,3 @@ -%Error: The following cannot be used together: --dpi-hdr-only, --lint-only, --xml-only, --json-only. Suggest see manual +%Error: The following cannot be used together: --dpi-hdr-only, --lint-only, --json-only. Suggest see manual ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_flag_only_bad3.py b/test_regress/t/t_flag_only_bad3.py index 6f0ee1fe6..4f58b51bb 100755 --- a/test_regress/t/t_flag_only_bad3.py +++ b/test_regress/t/t_flag_only_bad3.py @@ -13,7 +13,7 @@ test.scenarios('vlt') test.top_filename = "t/t_flag_main.v" test.lint( - verilator_flags2=["-Wall -Wno-DEPRECATED -Wno-fatal --dpi-hdr-only --xml-only --json-only"], + verilator_flags2=["-Wall -Wno-DEPRECATED -Wno-fatal --dpi-hdr-only --lint-only --json-only"], fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_var_port_xml.out b/test_regress/t/t_var_port_xml.out deleted file mode 100644 index 74a0b020e..000000000 --- a/test_regress/t/t_var_port_xml.out +++ /dev/null @@ -1,129 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/test_regress/t/t_var_port_xml.py b/test_regress/t/t_var_port_xml.py deleted file mode 100755 index 854552434..000000000 --- a/test_regress/t/t_var_port_xml.py +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt') - -out_filename = test.obj_dir + "/V" + test.name + ".xml" - -test.compile(verilator_flags2=['--no-std', '-Wno-DEPRECATED --xml-only', '--bbox-unsup'], - verilator_make_gmake=False, - make_top_shell=False, - make_main=False) - -test.files_identical(out_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_var_port_xml.v b/test_regress/t/t_var_port_xml.v deleted file mode 100644 index 88418b19c..000000000 --- a/test_regress/t/t_var_port_xml.v +++ /dev/null @@ -1,59 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2021 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -// This checks IEEE ports work correctly, we use XML output to make it easy to -// see all attributes are propagated - -// verilator lint_off MULTITOP - -`ifndef VERILATOR -module mh0 (wire x_inout_wire_logic); -endmodule -module mh1 (integer x_inout_wire_integer); -endmodule -`endif -module mh2 (inout integer x_inout_wire_integer); -endmodule -`ifndef VERILATOR -module mh3 ([5:0] x_inout_wire_logic_p6); -endmodule -`endif -module mh5 (input x_input_wire_logic); -endmodule -module mh6 (input var x_input_var_logic); -endmodule -module mh7 (input var integer x_input_var_integer); -endmodule -module mh8 (output x_output_wire_logic); -endmodule -module mh9 (output var x_output_var_logic); -endmodule -module mh10(output signed [5:0] x_output_wire_logic_signed_p6); -endmodule -module mh11(output integer x_output_var_integer); -endmodule -module mh12(ref [5:0] x_ref_logic_p6); -endmodule -module mh13(ref x_ref_var_logic_u6 [5:0]); -endmodule -`ifndef VERILATOR -module mh14(wire x_inout_wire_logic, y_inout_wire_logic_p8 [7:0]); -endmodule -module mh15(integer x_inout_wire_integer, signed [5:0] y_inout_wire_logic_signed6); -endmodule -module mh16([5:0] x_inout_wire_logic_p6, wire y_inout_wire_logic); -endmodule -`endif -module mh17(input var integer x_input_var_integer, wire y_input_wire_logic); -endmodule -module mh18(output var x_output_var_logic, input y_input_wire_logic); -endmodule -module mh19(output signed [5:0] x_output_wire_logic_signed_p6, integer y_output_var_integer); -endmodule -module mh20(ref [5:0] x_ref_var_logic_p6, y_ref_var_logic_p6); -endmodule -module mh21(ref ref_var_logic_u6 [5:0], y_ref_var_logic); -endmodule diff --git a/test_regress/t/t_xml_begin_hier.out b/test_regress/t/t_xml_begin_hier.out deleted file mode 100644 index efb01dd5f..000000000 --- a/test_regress/t/t_xml_begin_hier.out +++ /dev/null @@ -1,82 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/test_regress/t/t_xml_begin_hier.py b/test_regress/t/t_xml_begin_hier.py deleted file mode 100755 index 06a5adc58..000000000 --- a/test_regress/t/t_xml_begin_hier.py +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt') - -out_filename = test.obj_dir + "/V" + test.name + ".xml" - -test.compile(verilator_flags2=['--no-std', '-Wno-DEPRECATED --xml-only'], - verilator_make_gmake=False, - make_top_shell=False, - make_main=False) - -test.files_identical(out_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_xml_begin_hier.v b/test_regress/t/t_xml_begin_hier.v deleted file mode 100644 index 1e29f0133..000000000 --- a/test_regress/t/t_xml_begin_hier.v +++ /dev/null @@ -1,33 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Risto Pejasinovic. -// SPDX-License-Identifier: CC0-1.0 - -module submod2 (); -endmodule - -module submod #( -)(); - if(1) begin : submod_gen - wire l1_sig; - if(1) begin : nested_gen - submod2 submod_nested(); - end - submod2 submod_l1(); - end - submod2 submod_l0(); -endmodule - -module test( -); - genvar N; - generate for(N=0; N<2; N=N+1) - begin : FOR_GENERATE - submod submod_for(); - if(1) begin - submod submod_2(); - end - submod submod_3(); - end endgenerate -endmodule diff --git a/test_regress/t/t_xml_debugcheck.out b/test_regress/t/t_xml_debugcheck.out deleted file mode 100644 index 92e2667ae..000000000 --- a/test_regress/t/t_xml_debugcheck.out +++ /dev/null @@ -1,1854 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/test_regress/t/t_xml_debugcheck.py b/test_regress/t/t_xml_debugcheck.py deleted file mode 100755 index 000592728..000000000 --- a/test_regress/t/t_xml_debugcheck.py +++ /dev/null @@ -1,34 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt') -test.top_filename = "t/t_enum_type_methods.v" - -out_filename = test.obj_dir + "/V" + test.name + ".xml" - -test.compile(verilator_flags2=['--no-std', '--debug-check', '--flatten', '--inline-cfuncs', '0'], - verilator_make_gmake=False, - make_top_shell=False, - make_main=False) - -test.files_identical(out_filename, test.golden_filename, 'logfile') - -# make sure that certain tags are present in --debug-check -# that would not be present in --xml-only -test.file_grep(out_filename, r'') # for and -test.file_grep(out_filename, r' signed=') # for -test.file_grep(out_filename, r' func=') # for - -test.passes() diff --git a/test_regress/t/t_xml_deprecated_bad.out b/test_regress/t/t_xml_deprecated_bad.out deleted file mode 100644 index 838a455b0..000000000 --- a/test_regress/t/t_xml_deprecated_bad.out +++ /dev/null @@ -1,4 +0,0 @@ -%Warning-DEPRECATED: Option --xml-only is deprecated, move to --json-only - ... For warning description see https://verilator.org/warn/DEPRECATED?v=latest - ... Use "/* verilator lint_off DEPRECATED */" and lint_on around source to disable this message. -%Error: Exiting due to diff --git a/test_regress/t/t_xml_deprecated_bad.py b/test_regress/t/t_xml_deprecated_bad.py deleted file mode 100755 index 7d78f956d..000000000 --- a/test_regress/t/t_xml_deprecated_bad.py +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt') -test.top_filename = 't/t_EXAMPLE.v' - -test.compile(verilator_flags2=["--xml-only --xml-output /dev/null"], - fails=True, - expect_filename=test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_xml_first.out b/test_regress/t/t_xml_first.out deleted file mode 100644 index b7d6859a7..000000000 --- a/test_regress/t/t_xml_first.out +++ /dev/null @@ -1,88 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/test_regress/t/t_xml_first.py b/test_regress/t/t_xml_first.py deleted file mode 100755 index 06a5adc58..000000000 --- a/test_regress/t/t_xml_first.py +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt') - -out_filename = test.obj_dir + "/V" + test.name + ".xml" - -test.compile(verilator_flags2=['--no-std', '-Wno-DEPRECATED --xml-only'], - verilator_make_gmake=False, - make_top_shell=False, - make_main=False) - -test.files_identical(out_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_xml_first.v b/test_regress/t/t_xml_first.v deleted file mode 100644 index 7e594036d..000000000 --- a/test_regress/t/t_xml_first.v +++ /dev/null @@ -1,55 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2012 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -module t (/*AUTOARG*/ - // Outputs - q, - // Inputs - clk, d - ); - input clk; - input [3:0] d; - output wire [3:0] q; - - logic [3:0] between; - - mod1 #(.WIDTH(4)) - cell1 (.q(between), - .clk (clk), - .d (d[3:0])); - - mod2 - cell2 (.d(between), - .q (q[3:0]), - .clk (clk)); - -endmodule - -module mod1 - #(parameter WIDTH = 32) - ( - input clk, - input [WIDTH-1:0] d, - output logic [WIDTH-1:0] q - ); - - localparam IGNORED = 1; - - always @(posedge clk) - q <= d; - -endmodule - -module mod2 - ( - input clk, - input [3:0] d, - output wire [3:0] q - ); - - assign q = d; - -endmodule diff --git a/test_regress/t/t_xml_flat.out b/test_regress/t/t_xml_flat.out deleted file mode 100644 index 13058eb77..000000000 --- a/test_regress/t/t_xml_flat.out +++ /dev/null @@ -1,135 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/test_regress/t/t_xml_flat.py b/test_regress/t/t_xml_flat.py deleted file mode 100755 index 5c6842ae3..000000000 --- a/test_regress/t/t_xml_flat.py +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt') -test.top_filename = "t/t_xml_first.v" - -out_filename = test.obj_dir + "/V" + test.name + ".xml" - -test.compile(verilator_flags2=['--no-std', '-Wno-DEPRECATED --xml-only', '--flatten'], - verilator_make_gmake=False, - make_top_shell=False, - make_main=False) - -test.files_identical(out_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_xml_flat_no_inline_mod.out b/test_regress/t/t_xml_flat_no_inline_mod.out deleted file mode 100644 index 64359a65f..000000000 --- a/test_regress/t/t_xml_flat_no_inline_mod.out +++ /dev/null @@ -1,45 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/test_regress/t/t_xml_flat_no_inline_mod.py b/test_regress/t/t_xml_flat_no_inline_mod.py deleted file mode 100755 index 046b5ff50..000000000 --- a/test_regress/t/t_xml_flat_no_inline_mod.py +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt') - -out_filename = test.obj_dir + "/V" + test.name + ".xml" - -test.compile(verilator_flags2=['--no-std', '-Wno-DEPRECATED --xml-only', '--flatten'], - verilator_make_gmake=False, - make_top_shell=False, - make_main=False) - -test.files_identical(out_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_xml_flat_no_inline_mod.v b/test_regress/t/t_xml_flat_no_inline_mod.v deleted file mode 100644 index cf87b71a0..000000000 --- a/test_regress/t/t_xml_flat_no_inline_mod.v +++ /dev/null @@ -1,13 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -module foo(input logic i_clk); /* verilator no_inline_module */ -endmodule - -// --flatten forces inlining of 'no_inline_module' module foo. -module top(input logic i_clk); - foo f(.*); -endmodule diff --git a/test_regress/t/t_xml_flat_pub_mod.out b/test_regress/t/t_xml_flat_pub_mod.out deleted file mode 100644 index 68288d263..000000000 --- a/test_regress/t/t_xml_flat_pub_mod.out +++ /dev/null @@ -1,45 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/test_regress/t/t_xml_flat_pub_mod.py b/test_regress/t/t_xml_flat_pub_mod.py deleted file mode 100755 index 046b5ff50..000000000 --- a/test_regress/t/t_xml_flat_pub_mod.py +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt') - -out_filename = test.obj_dir + "/V" + test.name + ".xml" - -test.compile(verilator_flags2=['--no-std', '-Wno-DEPRECATED --xml-only', '--flatten'], - verilator_make_gmake=False, - make_top_shell=False, - make_main=False) - -test.files_identical(out_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_xml_flat_pub_mod.v b/test_regress/t/t_xml_flat_pub_mod.v deleted file mode 100644 index 4fa40e587..000000000 --- a/test_regress/t/t_xml_flat_pub_mod.v +++ /dev/null @@ -1,13 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -module foo(input logic i_clk); /* verilator public_module */ -endmodule - -// --flatten forces inlining of public module foo. -module top(input logic i_clk); - foo f(.*); -endmodule diff --git a/test_regress/t/t_xml_flat_vlvbound.out b/test_regress/t/t_xml_flat_vlvbound.out deleted file mode 100644 index 61b6d875d..000000000 --- a/test_regress/t/t_xml_flat_vlvbound.out +++ /dev/null @@ -1,220 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/test_regress/t/t_xml_flat_vlvbound.py b/test_regress/t/t_xml_flat_vlvbound.py deleted file mode 100755 index 046b5ff50..000000000 --- a/test_regress/t/t_xml_flat_vlvbound.py +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt') - -out_filename = test.obj_dir + "/V" + test.name + ".xml" - -test.compile(verilator_flags2=['--no-std', '-Wno-DEPRECATED --xml-only', '--flatten'], - verilator_make_gmake=False, - make_top_shell=False, - make_main=False) - -test.files_identical(out_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_xml_flat_vlvbound.v b/test_regress/t/t_xml_flat_vlvbound.v deleted file mode 100644 index 9ed0db0cf..000000000 --- a/test_regress/t/t_xml_flat_vlvbound.v +++ /dev/null @@ -1,27 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2012 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -module vlvbound_test - ( - input logic [15:0] i_a, - input logic [15:0] i_b, - output logic [6:0] o_a, - output logic [6:0] o_b - ); - - function automatic logic [6:0] foo(input logic [15:0] val); - logic [6:0] ret; - integer i; - for (i=0 ; i < 7; i++) begin - ret[i] = (val[i*2 +: 2] == 2'b00); - end - return ret; - endfunction - - assign o_a = foo(i_a); - assign o_b = foo(i_b); - -endmodule diff --git a/test_regress/t/t_xml_output.out b/test_regress/t/t_xml_output.out deleted file mode 100644 index 198efb7bc..000000000 --- a/test_regress/t/t_xml_output.out +++ /dev/null @@ -1,24 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/test_regress/t/t_xml_output.py b/test_regress/t/t_xml_output.py deleted file mode 100755 index 09f0d91b5..000000000 --- a/test_regress/t/t_xml_output.py +++ /dev/null @@ -1,31 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt') - -out_filename = test.obj_dir + "/renamed-" + test.name + ".xml" - -test.compile( - verilator_flags2=["--no-std", "-Wno-DEPRECATED --xml-only --xml-output", out_filename], - verilator_make_gmake=False, - make_top_shell=False, - make_main=False) - -test.files_identical(out_filename, test.golden_filename) - -for filename in test.glob_some(test.obj_dir + "/*"): - if (re.search(r'\.log', filename) # Made by driver.py, not Verilator sources - or re.search(r'\.status', filename) # Made by driver.py, not Verilator sources - or re.search(r'renamed-', filename)): # Requested output - continue - test.error("%Error: Created '" + filename + "', but --xml-only shouldn't create files") - -test.passes() diff --git a/test_regress/t/t_xml_output.v b/test_regress/t/t_xml_output.v deleted file mode 100644 index ccde3378d..000000000 --- a/test_regress/t/t_xml_output.v +++ /dev/null @@ -1,10 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -module m - (input clk); // verilator tag foo_op - -endmodule diff --git a/test_regress/t/t_xml_primary_io.out b/test_regress/t/t_xml_primary_io.out deleted file mode 100644 index 2b047aa91..000000000 --- a/test_regress/t/t_xml_primary_io.out +++ /dev/null @@ -1,62 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/test_regress/t/t_xml_primary_io.py b/test_regress/t/t_xml_primary_io.py deleted file mode 100755 index 1d5702fef..000000000 --- a/test_regress/t/t_xml_primary_io.py +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt') - -out_filename = test.obj_dir + "/V" + test.name + ".xml" - -test.compile(verilator_flags2=['--no-std', '-Wno-DEPRECATED --xml-only'], - verilator_make_gmake=False, - make_top_shell=False, - make_main=False) - -test.files_identical(out_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_xml_primary_io.v b/test_regress/t/t_xml_primary_io.v deleted file mode 100644 index 832cdb87e..000000000 --- a/test_regress/t/t_xml_primary_io.v +++ /dev/null @@ -1,30 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -module top(clk, a1, a2, ready); - input clk; - input a1; - input a2; - output ready; - - wire ready_reg; - - and2_x1 and_cell ( - .a1(a1), - .a2(a2), - .zn(ready_reg) - ); - - assign ready = ready_reg; -endmodule - -module and2_x1 ( - input wire a1, - input wire a2, - output wire zn -); - assign zn = (a1 & a2); -endmodule diff --git a/test_regress/t/t_xml_tag.out b/test_regress/t/t_xml_tag.out deleted file mode 100644 index f43c235e8..000000000 --- a/test_regress/t/t_xml_tag.out +++ /dev/null @@ -1,86 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/test_regress/t/t_xml_tag.py b/test_regress/t/t_xml_tag.py deleted file mode 100755 index 06a5adc58..000000000 --- a/test_regress/t/t_xml_tag.py +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt') - -out_filename = test.obj_dir + "/V" + test.name + ".xml" - -test.compile(verilator_flags2=['--no-std', '-Wno-DEPRECATED --xml-only'], - verilator_make_gmake=False, - make_top_shell=False, - make_main=False) - -test.files_identical(out_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_xml_tag.v b/test_regress/t/t_xml_tag.v deleted file mode 100644 index a47cd18d7..000000000 --- a/test_regress/t/t_xml_tag.v +++ /dev/null @@ -1,44 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Chris Randall. -// SPDX-License-Identifier: CC0-1.0 - -interface ifc; - integer value; - modport out_modport (output value); -endinterface - -module m - ( - input clk_ip, // verilator tag clk_ip - input rst_ip, - output foo_op); // verilator tag foo_op - - // This is a comment - - typedef struct packed { - logic clk; /* verilator tag this is clk */ - logic k; /* verilator lint_off UNUSED */ - logic enable; // verilator tag enable - logic data; // verilator tag data - } my_struct; // verilator tag my_struct - - // This is a comment - - ifc itop(); - - my_struct this_struct [2]; // verilator tag this_struct - - wire [31:0] dotted = itop.value; - - function void f(input string m); - $display("%s", m); - endfunction - - initial begin - // Contains all 256 characters except 0 (null character) - f("\x01\x02\x03\x04\x05\x06\a\x08\t\n\v\f\r\x0e\x0f\x10\x11\x12\x13\x14\x15\x16\x17\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f !\"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\\]^_`abcdefghijklmnopqrstuvwxyz{|}~\x7f\x80\x81\x82\x83\x84\x85\x86\x87\x88\x89\x8a\x8b\x8c\x8d\x8e\x8f\x90\x91\x92\x93\x94\x95\x96\x97\x98\x99\x9a\x9b\x9c\x9d\x9e\x9f\xa0\xa1\xa2\xa3\xa4\xa5\xa6\xa7\xa8\xa9\xaa\xab\xac\xad\xae\xaf\xb0\xb1\xb2\xb3\xb4\xb5\xb6\xb7\xb8\xb9\xba\xbb\xbc\xbd\xbe\xbf\xc0\xc1\xc2\xc3\xc4\xc5\xc6\xc7\xc8\xc9\xca\xcb\xcc\xcd\xce\xcf\xd0\xd1\xd2\xd3\xd4\xd5\xd6\xd7\xd8\xd9\xda\xdb\xdc\xdd\xde\xdf\xe0\xe1\xe2\xe3\xe4\xe5\xe6\xe7\xe8\xe9\xea\xeb\xec\xed\xee\xef\xf0\xf1\xf2\xf3\xf4\xf5\xf6\xf7\xf8\xf9\xfa\xfb\xfc\xfd\xfe\xff"); - end - -endmodule