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[#73220] remove processed tests

This commit is contained in:
Mateusz Gancarz 2025-02-25 15:30:03 +01:00
parent 72275448d3
commit a0d574e784
45 changed files with 1 additions and 1109 deletions
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39
test_regress/t/saif_tests/t_hier_block_sc_trace_saif.py
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@ -1,39 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt_all')
test.top_filename = "t/t_hier_block.v"
# stats will be deleted but generation will be skipped if libs of hierarchical blocks exist.
test.clean_objs()
# CI environment offers 2 VCPUs, 2 thread setting causes the following warning.
# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads.
# So use 6 threads here though it's not optimal in performance, but ok.
test.compile(v_flags2=['t/t_hier_block.cpp'],
verilator_flags2=[
'--sc', '--stats', '--hierarchical', '--CFLAGS', '"-pipe -DCPP_MACRO=cplusplus"',
"--CFLAGS", '"-O0 -ggdb"', "--trace-saif"
],
threads=(6 if test.vltmt else 1))
test.execute()
test.file_grep(test.obj_dir + "/Vsub0/sub0.sv", r'^module\s+(\S+)\s+', "sub0")
test.file_grep(test.obj_dir + "/Vsub1/sub1.sv", r'^module\s+(\S+)\s+', "sub1")
test.file_grep(test.obj_dir + "/Vsub2/sub2.sv", r'^module\s+(\S+)\s+', "sub2")
test.file_grep(test.stats, r'HierBlock,\s+Hierarchical blocks\s+(\d+)', 14)
test.file_grep(test.run_log_filename, r'MACRO:(\S+) is defined', "cplusplus")
test.saif_identical(test.trace_filename, test.golden_filename)
test.passes()

33
test_regress/t/saif_tests/t_hier_block_trace_saif.py
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@ -1,33 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt_all')
test.top_filename = "t/t_hier_block.v"
# CI environment offers 2 VCPUs, 2 thread setting causes the following warning.
# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads.
# So use 6 threads here though it's not optimal in performance, but ok.
test.compile(
v_flags2=['t/t_hier_block.cpp'],
verilator_flags2=[
'--hierarchical',
'--Wno-TIMESCALEMOD',
'--trace-saif',
'--no-trace-underscore', # To avoid handle mismatches
],
threads=(6 if test.vltmt else 1))
test.execute()
test.saif_identical(test.trace_filename, test.golden_filename)
test.passes()

21
test_regress/t/saif_tests/t_interface_ref_trace_saif.py
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@ -1,21 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.top_filename = "t/t_interface_ref_trace.v"
test.compile(verilator_flags2=['--trace-structs --trace-saif'])
test.execute()
test.saif_identical(test.trace_filename, test.golden_filename)
test.passes()

23
test_regress/t/saif_tests/t_interface_ref_trace_saif_sc.py
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@ -1,23 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.top_filename = "t/t_interface_ref_trace.v"
if not test.have_sc:
test.skip("No SystemC installed")
test.compile(verilator_flags2=['--trace-structs --trace-saif --sc'])
test.execute()
test.saif_identical(test.trace_filename, test.golden_filename)
test.passes()

21
test_regress/t/saif_tests/t_timing_trace_saif.py
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@ -1,21 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.top_filename = "t/t_timing_trace.v"
test.compile(verilator_flags2=["--exe --main --timing --trace-saif -Wno-MINTYPMAXDLY"])
test.execute()
test.saif_identical(test.trace_filename, test.golden_filename)
test.passes()

21
test_regress/t/saif_tests/t_trace_abort_saif.py
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@ -1,21 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt_all')
test.top_filename = "t/t_trace_abort.v"
test.compile(verilator_flags2=['--cc --trace-saif'])
test.execute(fails=True)
test.saif_identical(test.trace_filename, test.golden_filename)
test.passes()

24
test_regress/t/saif_tests/t_trace_abort_saif_sc.py
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@ -1,24 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt_all')
test.top_filename = "t/t_trace_abort.v"
if not test.have_sc:
test.skip("No SystemC installed")
test.compile(verilator_flags2=['--sc --trace-saif'])
test.execute(fails=True)
test.saif_identical(test.trace_filename, test.golden_filename)
test.passes()

21
test_regress/t/saif_tests/t_trace_array_saif.py
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@ -1,21 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt')
test.top_filename = "t/t_trace_array.v"
test.compile(verilator_flags2=['--cc --trace-saif --trace-structs'])
test.execute()
test.saif_identical(test.trace_filename, test.golden_filename)
test.passes()

22
test_regress/t/saif_tests/t_trace_array_saif_portable.py
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@ -1,22 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt')
test.top_filename = "t/t_trace_array.v"
test.golden_filename = "t/t_trace_array_fst.out"
test.compile(verilator_flags2=['--cc --trace-saif --trace-structs', '-CFLAGS -DVL_PORTABLE_ONLY'])
test.execute()
test.saif_identical(test.trace_filename, test.golden_filename)
test.passes()

25
test_regress/t/saif_tests/t_trace_array_saif_portable_sc.py
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@ -1,25 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt')
test.top_filename = "t/t_trace_array.v"
test.golden_filename = "t/t_trace_array_fst_sc.out"
if not test.have_sc:
test.skip("No SystemC installed")
test.compile(verilator_flags2=['--sc --trace-saif --trace-structs', '-CFLAGS -DVL_PORTABLE_ONLY'])
test.execute()
test.saif_identical(test.trace_filename, test.golden_filename)
test.passes()

24
test_regress/t/saif_tests/t_trace_array_saif_sc.py
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@ -1,24 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt')
test.top_filename = "t/t_trace_array.v"
if not test.have_sc:
test.skip("No SystemC installed")
test.compile(verilator_flags2=['--sc --trace-saif --trace-structs'])
test.execute()
test.saif_identical(test.trace_filename, test.golden_filename)
test.passes()

22
test_regress/t/saif_tests/t_trace_array_saif_threads_1.py
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@ -1,22 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt')
test.top_filename = "t/t_trace_array.v"
test.golden_filename = "t/t_trace_array_fst.out"
test.compile(verilator_flags2=['--cc --trace-saif --trace-threads 1 --trace-structs'])
test.execute()
test.saif_identical(test.trace_filename, test.golden_filename)
test.passes()

25
test_regress/t/saif_tests/t_trace_array_saif_threads_1_sc.py
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@ -1,25 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt')
test.top_filename = "t/t_trace_array.v"
test.golden_filename = "t/t_trace_array_fst_sc.out"
if not test.have_sc:
test.skip("No SystemC installed")
test.compile(verilator_flags2=['--sc --trace-saif --trace-threads 1 --trace-structs'])
test.execute()
test.saif_identical(test.trace_filename, test.golden_filename)
test.passes()

22
test_regress/t/saif_tests/t_trace_array_saif_threads_2.py
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@ -1,22 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt')
test.top_filename = "t/t_trace_array.v"
test.golden_filename = "t/t_trace_array_fst.out"
test.compile(verilator_flags2=['--cc --trace-saif --trace-threads 2 --trace-structs'])
test.execute()
test.saif_identical(test.trace_filename, test.golden_filename)
test.passes()

25
test_regress/t/saif_tests/t_trace_array_saif_threads_2_sc.py
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@ -1,25 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt')
test.top_filename = "t/t_trace_array.v"
test.golden_filename = "t/t_trace_array_fst_sc.out"
if not test.have_sc:
test.skip("No SystemC installed")
test.compile(verilator_flags2=['--sc --trace-saif --trace-threads 2 --trace-structs'])
test.execute()
test.saif_identical(test.trace_filename, test.golden_filename)
test.passes()

25
test_regress/t/saif_tests/t_trace_ascendingrange_saif.py
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@ -1,25 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.top_filename = "t/t_trace_ascendingrange.v"
# CI environment offers 2 VCPUs, 2 thread setting causes the following warning.
# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads.
# Strangely, asking for more threads makes it go away.
test.compile(verilator_flags2=['--cc --trace-saif --trace-params -Wno-ASCRANGE'],
threads=(6 if test.vltmt else 1))
test.execute()
test.saif_identical(test.trace_filename, test.golden_filename)
test.passes()

28
test_regress/t/saif_tests/t_trace_ascendingrange_saif_sc.py
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@ -1,28 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.top_filename = "t/t_trace_ascendingrange.v"
if not test.have_sc:
test.skip("No SystemC installed")
# CI environment offers 2 VCPUs, 2 thread setting causes the following warning.
# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads.
# Strangely, asking for more threads makes it go away.
test.compile(verilator_flags2=['--sc --trace-saif --trace-params -Wno-ASCRANGE'],
threads=(6 if test.vltmt else 1))
test.execute()
test.saif_identical(test.trace_filename, test.golden_filename)
test.passes()

25
test_regress/t/saif_tests/t_trace_cat_saif.py
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@ -1,25 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt_all')
test.top_filename = "t/t_trace_cat_fst.v"
test.compile(make_top_shell=False,
make_main=False,
v_flags2=["--trace-saif --exe", test.pli_filename])
test.execute()
test.saif_identical(test.obj_dir + "/simpart_0000.saif", "t/" + test.name + "_0000.saif")
test.saif_identical(test.obj_dir + "/simpart_0100.saif", "t/" + test.name + "_0100.saif")
test.passes()

21
test_regress/t/saif_tests/t_trace_complex_params_saif.py
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@ -1,21 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.top_filename = "t/t_trace_complex.v"
test.compile(verilator_flags2=['--cc --trace-saif --no-trace-structs --trace-params'])
test.execute()
test.saif_identical(test.trace_filename, test.golden_filename)
test.passes()

24
test_regress/t/saif_tests/t_trace_complex_params_saif_sc.py
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@ -1,24 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.top_filename = "t/t_trace_complex.v"
if not test.have_sc:
test.skip("No SystemC installed")
test.compile(verilator_flags2=['--sc --trace-saif --no-trace-structs --trace-params'])
test.execute()
test.saif_identical(test.trace_filename, test.golden_filename)
test.passes()

21
test_regress/t/saif_tests/t_trace_complex_saif.py
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@ -1,21 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.top_filename = "t/t_trace_complex.v"
test.compile(verilator_flags2=['--cc --trace-saif'])
test.execute()
test.saif_identical(test.trace_filename, test.golden_filename)
test.passes()

24
test_regress/t/saif_tests/t_trace_complex_saif_sc.py
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@ -1,24 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.top_filename = "t/t_trace_complex.v"
if not test.have_sc:
test.skip("No SystemC installed")
test.compile(verilator_flags2=['--sc --trace-saif'])
test.execute()
test.saif_identical(test.trace_filename, test.golden_filename)
test.passes()

22
test_regress/t/saif_tests/t_trace_complex_saif_threads_1.py
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@ -1,22 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.top_filename = "t/t_trace_complex.v"
test.golden_filename = "t/t_trace_complex_fst.out"
test.compile(verilator_flags2=['--cc --trace-saif --trace-threads 1'])
test.execute()
test.saif_identical(test.trace_filename, test.golden_filename)
test.passes()

25
test_regress/t/saif_tests/t_trace_complex_saif_threads_1_sc.py
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@ -1,25 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.top_filename = "t/t_trace_complex.v"
test.golden_filename = "t/t_trace_complex_fst_sc.out"
if not test.have_sc:
test.skip("No SystemC installed")
test.compile(verilator_flags2=['--sc --trace-saif --trace-threads 1'])
test.execute()
test.saif_identical(test.trace_filename, test.golden_filename)
test.passes()

22
test_regress/t/saif_tests/t_trace_complex_saif_threads_2.py
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@ -1,22 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.top_filename = "t/t_trace_complex.v"
test.golden_filename = "t/t_trace_complex_fst.out"
test.compile(verilator_flags2=['--cc --trace-saif --trace-threads 2'])
test.execute()
test.saif_identical(test.trace_filename, test.golden_filename)
test.passes()

25
test_regress/t/saif_tests/t_trace_complex_saif_threads_2_sc.py
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@ -1,25 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.top_filename = "t/t_trace_complex.v"
test.golden_filename = "t/t_trace_complex_fst_sc.out"
if not test.have_sc:
test.skip("No SystemC installed")
test.compile(verilator_flags2=['--sc --trace-saif --trace-threads 2'])
test.execute()
test.saif_identical(test.trace_filename, test.golden_filename)
test.passes()

21
test_regress/t/saif_tests/t_trace_complex_structs_saif.py
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@ -1,21 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.top_filename = "t/t_trace_complex.v"
test.compile(verilator_flags2=['--cc --trace-saif --trace-structs --no-trace-params'])
test.execute()
test.saif_identical(test.trace_filename, test.golden_filename)
test.passes()

24
test_regress/t/saif_tests/t_trace_complex_structs_saif_sc.py
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@ -1,24 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.top_filename = "t/t_trace_complex.v"
if not test.have_sc:
test.skip("No SystemC installed")
test.compile(verilator_flags2=['--sc --trace-saif --trace-structs --no-trace-params'])
test.execute()
test.saif_identical(test.trace_filename, test.golden_filename)
test.passes()

22
test_regress/t/saif_tests/t_trace_counter_saif.py
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@ -1,22 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test module
#
# Copyright 2025 by Antmicro. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt')
test.top_filename = "t/t_trace_counter.v"
test.compile(verilator_flags2=['--cc --trace'])
test.execute()
#TODO: add function checking if two SAIF files are identical
#test.saif_identical(test.trace_filename, test.golden_filename)
test.passes()

22
test_regress/t/saif_tests/t_trace_dumpvars_dyn_saif_0.py
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@ -1,22 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt_all')
test.pli_filename = "t/t_trace_dumpvars_dyn.cpp"
test.top_filename = "t/t_trace_dumpvars_dyn.v"
test.compile(make_main=False, verilator_flags2=["--trace-saif --exe", test.pli_filename])
test.execute()
test.saif_identical(test.trace_filename, test.golden_filename)
test.passes()

22
test_regress/t/saif_tests/t_trace_dumpvars_dyn_saif_1.py
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@ -1,22 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt_all')
test.pli_filename = "t/t_trace_dumpvars_dyn.cpp"
test.top_filename = "t/t_trace_dumpvars_dyn.v"
test.compile(make_main=False, verilator_flags2=["--trace-saif --exe", test.pli_filename])
test.execute()
test.saif_identical(test.trace_filename, test.golden_filename)
test.passes()

29
test_regress/t/saif_tests/t_trace_enum_saif.py
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@ -1,29 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.top_filename = "t/t_trace_enum.v"
test.compile(verilator_flags2=['--cc --trace-saif --output-split-ctrace 1'])
test.execute()
test.saif_identical(test.trace_filename, test.golden_filename)
# Five $attrbegin expected:
# - state_t declaration
# - t.v_enumed
# - t.sink.state
# - other_state_t declaration
# - t.v_other_enumed
test.file_grep_count(test.golden_filename, r'attrbegin', 5)
test.passes()

22
test_regress/t/saif_tests/t_trace_jumps_do_while_saif.py
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@ -1,22 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test module
#
# Copyright 2025 by Antmicro. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt')
test.top_filename = "t/t_jumps_do_while.v"
test.compile(verilator_flags2=['--trace-saif'])
test.execute()
#TODO: add function checking if two SAIF files are identical
#test.saif_identical(test.trace_filename, test.golden_filename)
test.passes()

22
test_regress/t/saif_tests/t_trace_no_top_name2_saif.py
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@ -1,22 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt')
test.pli_filename = "t/t_trace_no_top_name2.cpp"
test.top_filename = "t/t_trace_no_top_name2.v"
test.compile(make_main=False, verilator_flags2=["--trace-saif --exe", test.pli_filename])
test.execute()
test.saif_identical(test.trace_filename, test.golden_filename)
test.passes()

21
test_regress/t/saif_tests/t_trace_packed_struct_saif.py
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@ -1,21 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.top_filename = "t/t_trace_packed_struct.v"
test.compile(v_flags2=["--trace-saif"])
test.execute()
test.saif_identical(test.trace_filename, test.golden_filename)
test.passes()

24
test_regress/t/saif_tests/t_trace_packed_struct_saif_sc.py
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@ -1,24 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.top_filename = "t/t_trace_packed_struct.v"
if not test.have_sc:
test.skip("No SystemC installed")
test.compile(v_flags2=["--sc --trace-saif"])
test.execute()
test.saif_identical(test.trace_filename, test.golden_filename)
test.passes()

19
test_regress/t/saif_tests/t_trace_param_saif.py
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@ -1,19 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt_all')
test.top_filename = "t/t_trace_param.v"
test.compile(v_flags2=["--trace-saif"])
test.execute()
test.passes()

19
test_regress/t/saif_tests/t_trace_primitive_saif.py
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@ -1,19 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.top_filename = "t/t_trace_primitive.v"
test.compile(v_flags2=["--trace-saif"])
test.execute()
test.passes()

22
test_regress/t/saif_tests/t_trace_primitive_saif_sc.py
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@ -1,22 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.top_filename = "t/t_trace_primitive.v"
if not test.have_sc:
test.skip("No SystemC installed")
test.compile(v_flags2=["--sc --trace-saif"])
test.execute()
test.passes()

20
test_regress/t/saif_tests/t_trace_saif.py
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@ -1,20 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt_all')
test.compile(v_flags2=["--trace-saif"])
test.execute()
test.saif_identical(test.trace_filename, test.golden_filename)
test.passes()

99
test_regress/t/saif_tests/t_trace_saif.v
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@ -1,99 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// Author: Yu-Sheng Lin johnjohnlys@media.ee.ntu.edu.tw
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Outputs
state,
// Inputs
clk
);
input clk;
int cyc;
reg rstn;
output [4:0] state;
parameter real fst_gparam_real = 1.23;
localparam real fst_lparam_real = 4.56;
real fst_real = 1.23;
integer fst_integer;
bit fst_bit;
logic fst_logic;
int fst_int;
shortint fst_shortint;
longint fst_longint;
byte fst_byte;
parameter fst_parameter = 123;
localparam fst_lparam = 456;
supply0 fst_supply0;
supply1 fst_supply1;
tri0 fst_tri0;
tri1 fst_tri1;
tri fst_tri;
wire fst_wire;
Test test (/*AUTOINST*/
// Outputs
.state (state[4:0]),
// Inputs
.clk (clk),
.rstn (rstn));
// Test loop
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==0) begin
// Setup
rstn <= ~'1;
end
else if (cyc<10) begin
rstn <= ~'1;
end
else if (cyc<90) begin
rstn <= ~'0;
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (
input clk,
input rstn,
output logic [4:0] state
);
logic [4:0] state_w;
logic [4:0] state_array [3];
assign state = state_array[0];
always_comb begin
state_w[4] = state_array[2][0];
state_w[3] = state_array[2][4];
state_w[2] = state_array[2][3] ^ state_array[2][0];
state_w[1] = state_array[2][2];
state_w[0] = state_array[2][1];
end
always_ff @(posedge clk or negedge rstn) begin
if (!rstn) begin
for (int i = 0; i < 3; i++)
state_array[i] <= 'b1;
end
else begin
for (int i = 0; i < 2; i++)
state_array[i] <= state_array[i+1];
state_array[2] <= state_w;
end
end
endmodule

23
test_regress/t/saif_tests/t_trace_saif_sc.py
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@ -1,23 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt_all')
if not test.have_sc:
test.skip("No SystemC installed")
test.compile(verilator_flags2=["--trace-saif --sc"])
test.execute()
test.saif_identical(test.trace_filename, test.golden_filename)
test.passes()

25
test_regress/t/saif_tests/t_trace_saif_sc_cmake.py
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@ -1,25 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt_all')
if not test.have_sc:
test.skip("No SystemC installed")
test.compile(verilator_flags2=["--trace-saif --sc"],
verilator_make_gmake=False,
verilator_make_cmake=1)
test.execute()
test.saif_identical(test.trace_filename, test.golden_filename)
test.passes()

2
test_regress/t/saif_tests/t_trace_string_saif.py
View File

@ -12,7 +12,7 @@ import vltest_bootstrap
test.scenarios('simulator')
test.top_filename = "t/t_trace_string.v"
test.compile(verilator_flags2=['--cc --trace'])
test.compile(verilator_flags2=['--cc --trace-saif'])
test.execute()

22
test_regress/t/saif_tests/t_trace_string_saif_sc.py
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@ -1,22 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.top_filename = "t/t_trace_string.v"
if not test.have_sc:
test.skip("No SystemC installed")
test.compile(verilator_flags2=['--sc --trace'])
test.execute()
test.passes()