From a0d574e784835bf460fe0c40564019a26d6c0d9f Mon Sep 17 00:00:00 2001 From: Mateusz Gancarz Date: Tue, 25 Feb 2025 15:30:03 +0100 Subject: [PATCH] [#73220] remove processed tests --- .../saif_tests/t_hier_block_sc_trace_saif.py | 39 -------- .../t/saif_tests/t_hier_block_trace_saif.py | 33 ------- .../saif_tests/t_interface_ref_trace_saif.py | 21 ---- .../t_interface_ref_trace_saif_sc.py | 23 ----- .../t/saif_tests/t_timing_trace_saif.py | 21 ---- .../t/saif_tests/t_trace_abort_saif.py | 21 ---- .../t/saif_tests/t_trace_abort_saif_sc.py | 24 ----- .../t/saif_tests/t_trace_array_saif.py | 21 ---- .../saif_tests/t_trace_array_saif_portable.py | 22 ----- .../t_trace_array_saif_portable_sc.py | 25 ----- .../t/saif_tests/t_trace_array_saif_sc.py | 24 ----- .../t_trace_array_saif_threads_1.py | 22 ----- .../t_trace_array_saif_threads_1_sc.py | 25 ----- .../t_trace_array_saif_threads_2.py | 22 ----- .../t_trace_array_saif_threads_2_sc.py | 25 ----- .../saif_tests/t_trace_ascendingrange_saif.py | 25 ----- .../t_trace_ascendingrange_saif_sc.py | 28 ------ test_regress/t/saif_tests/t_trace_cat_saif.py | 25 ----- .../saif_tests/t_trace_complex_params_saif.py | 21 ---- .../t_trace_complex_params_saif_sc.py | 24 ----- .../t/saif_tests/t_trace_complex_saif.py | 21 ---- .../t/saif_tests/t_trace_complex_saif_sc.py | 24 ----- .../t_trace_complex_saif_threads_1.py | 22 ----- .../t_trace_complex_saif_threads_1_sc.py | 25 ----- .../t_trace_complex_saif_threads_2.py | 22 ----- .../t_trace_complex_saif_threads_2_sc.py | 25 ----- .../t_trace_complex_structs_saif.py | 21 ---- .../t_trace_complex_structs_saif_sc.py | 24 ----- .../t/saif_tests/t_trace_counter_saif.py | 22 ----- .../saif_tests/t_trace_dumpvars_dyn_saif_0.py | 22 ----- .../saif_tests/t_trace_dumpvars_dyn_saif_1.py | 22 ----- .../t/saif_tests/t_trace_enum_saif.py | 29 ------ .../saif_tests/t_trace_jumps_do_while_saif.py | 22 ----- .../t/saif_tests/t_trace_no_top_name2_saif.py | 22 ----- .../saif_tests/t_trace_packed_struct_saif.py | 21 ---- .../t_trace_packed_struct_saif_sc.py | 24 ----- .../t/saif_tests/t_trace_param_saif.py | 19 ---- .../t/saif_tests/t_trace_primitive_saif.py | 19 ---- .../t/saif_tests/t_trace_primitive_saif_sc.py | 22 ----- test_regress/t/saif_tests/t_trace_saif.py | 20 ---- test_regress/t/saif_tests/t_trace_saif.v | 99 ------------------- test_regress/t/saif_tests/t_trace_saif_sc.py | 23 ----- .../t/saif_tests/t_trace_saif_sc_cmake.py | 25 ----- .../t/saif_tests/t_trace_string_saif.py | 2 +- .../t/saif_tests/t_trace_string_saif_sc.py | 22 ----- 45 files changed, 1 insertion(+), 1109 deletions(-) delete mode 100755 test_regress/t/saif_tests/t_hier_block_sc_trace_saif.py delete mode 100755 test_regress/t/saif_tests/t_hier_block_trace_saif.py delete mode 100755 test_regress/t/saif_tests/t_interface_ref_trace_saif.py delete mode 100755 test_regress/t/saif_tests/t_interface_ref_trace_saif_sc.py delete mode 100755 test_regress/t/saif_tests/t_timing_trace_saif.py delete mode 100755 test_regress/t/saif_tests/t_trace_abort_saif.py delete mode 100755 test_regress/t/saif_tests/t_trace_abort_saif_sc.py delete mode 100755 test_regress/t/saif_tests/t_trace_array_saif.py delete mode 100755 test_regress/t/saif_tests/t_trace_array_saif_portable.py delete mode 100755 test_regress/t/saif_tests/t_trace_array_saif_portable_sc.py delete mode 100755 test_regress/t/saif_tests/t_trace_array_saif_sc.py delete mode 100755 test_regress/t/saif_tests/t_trace_array_saif_threads_1.py delete mode 100755 test_regress/t/saif_tests/t_trace_array_saif_threads_1_sc.py delete mode 100755 test_regress/t/saif_tests/t_trace_array_saif_threads_2.py delete mode 100755 test_regress/t/saif_tests/t_trace_array_saif_threads_2_sc.py delete mode 100755 test_regress/t/saif_tests/t_trace_ascendingrange_saif.py delete mode 100755 test_regress/t/saif_tests/t_trace_ascendingrange_saif_sc.py delete mode 100755 test_regress/t/saif_tests/t_trace_cat_saif.py delete mode 100755 test_regress/t/saif_tests/t_trace_complex_params_saif.py delete mode 100755 test_regress/t/saif_tests/t_trace_complex_params_saif_sc.py delete mode 100755 test_regress/t/saif_tests/t_trace_complex_saif.py delete mode 100755 test_regress/t/saif_tests/t_trace_complex_saif_sc.py delete mode 100755 test_regress/t/saif_tests/t_trace_complex_saif_threads_1.py delete mode 100755 test_regress/t/saif_tests/t_trace_complex_saif_threads_1_sc.py delete mode 100755 test_regress/t/saif_tests/t_trace_complex_saif_threads_2.py delete mode 100755 test_regress/t/saif_tests/t_trace_complex_saif_threads_2_sc.py delete mode 100755 test_regress/t/saif_tests/t_trace_complex_structs_saif.py delete mode 100755 test_regress/t/saif_tests/t_trace_complex_structs_saif_sc.py delete mode 100755 test_regress/t/saif_tests/t_trace_counter_saif.py delete mode 100755 test_regress/t/saif_tests/t_trace_dumpvars_dyn_saif_0.py delete mode 100755 test_regress/t/saif_tests/t_trace_dumpvars_dyn_saif_1.py delete mode 100755 test_regress/t/saif_tests/t_trace_enum_saif.py delete mode 100755 test_regress/t/saif_tests/t_trace_jumps_do_while_saif.py delete mode 100755 test_regress/t/saif_tests/t_trace_no_top_name2_saif.py delete mode 100755 test_regress/t/saif_tests/t_trace_packed_struct_saif.py delete mode 100755 test_regress/t/saif_tests/t_trace_packed_struct_saif_sc.py delete mode 100755 test_regress/t/saif_tests/t_trace_param_saif.py delete mode 100755 test_regress/t/saif_tests/t_trace_primitive_saif.py delete mode 100755 test_regress/t/saif_tests/t_trace_primitive_saif_sc.py delete mode 100755 test_regress/t/saif_tests/t_trace_saif.py delete mode 100644 test_regress/t/saif_tests/t_trace_saif.v delete mode 100755 test_regress/t/saif_tests/t_trace_saif_sc.py delete mode 100755 test_regress/t/saif_tests/t_trace_saif_sc_cmake.py delete mode 100755 test_regress/t/saif_tests/t_trace_string_saif_sc.py diff --git a/test_regress/t/saif_tests/t_hier_block_sc_trace_saif.py b/test_regress/t/saif_tests/t_hier_block_sc_trace_saif.py deleted file mode 100755 index 8380974c7..000000000 --- a/test_regress/t/saif_tests/t_hier_block_sc_trace_saif.py +++ /dev/null @@ -1,39 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt_all') -test.top_filename = "t/t_hier_block.v" - -# stats will be deleted but generation will be skipped if libs of hierarchical blocks exist. -test.clean_objs() - -# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. -# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. -# So use 6 threads here though it's not optimal in performance, but ok. - -test.compile(v_flags2=['t/t_hier_block.cpp'], - verilator_flags2=[ - '--sc', '--stats', '--hierarchical', '--CFLAGS', '"-pipe -DCPP_MACRO=cplusplus"', - "--CFLAGS", '"-O0 -ggdb"', "--trace-saif" - ], - threads=(6 if test.vltmt else 1)) - -test.execute() - -test.file_grep(test.obj_dir + "/Vsub0/sub0.sv", r'^module\s+(\S+)\s+', "sub0") -test.file_grep(test.obj_dir + "/Vsub1/sub1.sv", r'^module\s+(\S+)\s+', "sub1") -test.file_grep(test.obj_dir + "/Vsub2/sub2.sv", r'^module\s+(\S+)\s+', "sub2") -test.file_grep(test.stats, r'HierBlock,\s+Hierarchical blocks\s+(\d+)', 14) -test.file_grep(test.run_log_filename, r'MACRO:(\S+) is defined', "cplusplus") - -test.saif_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/saif_tests/t_hier_block_trace_saif.py b/test_regress/t/saif_tests/t_hier_block_trace_saif.py deleted file mode 100755 index 254156804..000000000 --- a/test_regress/t/saif_tests/t_hier_block_trace_saif.py +++ /dev/null @@ -1,33 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt_all') -test.top_filename = "t/t_hier_block.v" - -# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. -# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. -# So use 6 threads here though it's not optimal in performance, but ok. - -test.compile( - v_flags2=['t/t_hier_block.cpp'], - verilator_flags2=[ - '--hierarchical', - '--Wno-TIMESCALEMOD', - '--trace-saif', - '--no-trace-underscore', # To avoid handle mismatches - ], - threads=(6 if test.vltmt else 1)) - -test.execute() - -test.saif_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/saif_tests/t_interface_ref_trace_saif.py b/test_regress/t/saif_tests/t_interface_ref_trace_saif.py deleted file mode 100755 index 3ebe41194..000000000 --- a/test_regress/t/saif_tests/t_interface_ref_trace_saif.py +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') -test.top_filename = "t/t_interface_ref_trace.v" - -test.compile(verilator_flags2=['--trace-structs --trace-saif']) - -test.execute() - -test.saif_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/saif_tests/t_interface_ref_trace_saif_sc.py b/test_regress/t/saif_tests/t_interface_ref_trace_saif_sc.py deleted file mode 100755 index 9015b11dd..000000000 --- a/test_regress/t/saif_tests/t_interface_ref_trace_saif_sc.py +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') -test.top_filename = "t/t_interface_ref_trace.v" - -if not test.have_sc: - test.skip("No SystemC installed") - -test.compile(verilator_flags2=['--trace-structs --trace-saif --sc']) - -test.execute() - -test.saif_identical(test.trace_filename, test.golden_filename) -test.passes() diff --git a/test_regress/t/saif_tests/t_timing_trace_saif.py b/test_regress/t/saif_tests/t_timing_trace_saif.py deleted file mode 100755 index b5bd921eb..000000000 --- a/test_regress/t/saif_tests/t_timing_trace_saif.py +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') -test.top_filename = "t/t_timing_trace.v" - -test.compile(verilator_flags2=["--exe --main --timing --trace-saif -Wno-MINTYPMAXDLY"]) - -test.execute() - -test.saif_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/saif_tests/t_trace_abort_saif.py b/test_regress/t/saif_tests/t_trace_abort_saif.py deleted file mode 100755 index 2053a1bcd..000000000 --- a/test_regress/t/saif_tests/t_trace_abort_saif.py +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt_all') -test.top_filename = "t/t_trace_abort.v" - -test.compile(verilator_flags2=['--cc --trace-saif']) - -test.execute(fails=True) - -test.saif_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/saif_tests/t_trace_abort_saif_sc.py b/test_regress/t/saif_tests/t_trace_abort_saif_sc.py deleted file mode 100755 index 3bdffa73d..000000000 --- a/test_regress/t/saif_tests/t_trace_abort_saif_sc.py +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt_all') -test.top_filename = "t/t_trace_abort.v" - -if not test.have_sc: - test.skip("No SystemC installed") - -test.compile(verilator_flags2=['--sc --trace-saif']) - -test.execute(fails=True) - -test.saif_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/saif_tests/t_trace_array_saif.py b/test_regress/t/saif_tests/t_trace_array_saif.py deleted file mode 100755 index e9a4c8abc..000000000 --- a/test_regress/t/saif_tests/t_trace_array_saif.py +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt') -test.top_filename = "t/t_trace_array.v" - -test.compile(verilator_flags2=['--cc --trace-saif --trace-structs']) - -test.execute() - -test.saif_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/saif_tests/t_trace_array_saif_portable.py b/test_regress/t/saif_tests/t_trace_array_saif_portable.py deleted file mode 100755 index 73fa92133..000000000 --- a/test_regress/t/saif_tests/t_trace_array_saif_portable.py +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt') -test.top_filename = "t/t_trace_array.v" -test.golden_filename = "t/t_trace_array_fst.out" - -test.compile(verilator_flags2=['--cc --trace-saif --trace-structs', '-CFLAGS -DVL_PORTABLE_ONLY']) - -test.execute() - -test.saif_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/saif_tests/t_trace_array_saif_portable_sc.py b/test_regress/t/saif_tests/t_trace_array_saif_portable_sc.py deleted file mode 100755 index 6dfeee2ab..000000000 --- a/test_regress/t/saif_tests/t_trace_array_saif_portable_sc.py +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt') -test.top_filename = "t/t_trace_array.v" -test.golden_filename = "t/t_trace_array_fst_sc.out" - -if not test.have_sc: - test.skip("No SystemC installed") - -test.compile(verilator_flags2=['--sc --trace-saif --trace-structs', '-CFLAGS -DVL_PORTABLE_ONLY']) - -test.execute() - -test.saif_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/saif_tests/t_trace_array_saif_sc.py b/test_regress/t/saif_tests/t_trace_array_saif_sc.py deleted file mode 100755 index 0b6db4657..000000000 --- a/test_regress/t/saif_tests/t_trace_array_saif_sc.py +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt') -test.top_filename = "t/t_trace_array.v" - -if not test.have_sc: - test.skip("No SystemC installed") - -test.compile(verilator_flags2=['--sc --trace-saif --trace-structs']) - -test.execute() - -test.saif_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/saif_tests/t_trace_array_saif_threads_1.py b/test_regress/t/saif_tests/t_trace_array_saif_threads_1.py deleted file mode 100755 index 71b7fd55d..000000000 --- a/test_regress/t/saif_tests/t_trace_array_saif_threads_1.py +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt') -test.top_filename = "t/t_trace_array.v" -test.golden_filename = "t/t_trace_array_fst.out" - -test.compile(verilator_flags2=['--cc --trace-saif --trace-threads 1 --trace-structs']) - -test.execute() - -test.saif_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/saif_tests/t_trace_array_saif_threads_1_sc.py b/test_regress/t/saif_tests/t_trace_array_saif_threads_1_sc.py deleted file mode 100755 index b30a0e210..000000000 --- a/test_regress/t/saif_tests/t_trace_array_saif_threads_1_sc.py +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt') -test.top_filename = "t/t_trace_array.v" -test.golden_filename = "t/t_trace_array_fst_sc.out" - -if not test.have_sc: - test.skip("No SystemC installed") - -test.compile(verilator_flags2=['--sc --trace-saif --trace-threads 1 --trace-structs']) - -test.execute() - -test.saif_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/saif_tests/t_trace_array_saif_threads_2.py b/test_regress/t/saif_tests/t_trace_array_saif_threads_2.py deleted file mode 100755 index 569f92e48..000000000 --- a/test_regress/t/saif_tests/t_trace_array_saif_threads_2.py +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt') -test.top_filename = "t/t_trace_array.v" -test.golden_filename = "t/t_trace_array_fst.out" - -test.compile(verilator_flags2=['--cc --trace-saif --trace-threads 2 --trace-structs']) - -test.execute() - -test.saif_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/saif_tests/t_trace_array_saif_threads_2_sc.py b/test_regress/t/saif_tests/t_trace_array_saif_threads_2_sc.py deleted file mode 100755 index c7f999671..000000000 --- a/test_regress/t/saif_tests/t_trace_array_saif_threads_2_sc.py +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt') -test.top_filename = "t/t_trace_array.v" -test.golden_filename = "t/t_trace_array_fst_sc.out" - -if not test.have_sc: - test.skip("No SystemC installed") - -test.compile(verilator_flags2=['--sc --trace-saif --trace-threads 2 --trace-structs']) - -test.execute() - -test.saif_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/saif_tests/t_trace_ascendingrange_saif.py b/test_regress/t/saif_tests/t_trace_ascendingrange_saif.py deleted file mode 100755 index 10e5f248e..000000000 --- a/test_regress/t/saif_tests/t_trace_ascendingrange_saif.py +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') -test.top_filename = "t/t_trace_ascendingrange.v" - -# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. -# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. -# Strangely, asking for more threads makes it go away. -test.compile(verilator_flags2=['--cc --trace-saif --trace-params -Wno-ASCRANGE'], - threads=(6 if test.vltmt else 1)) - -test.execute() - -test.saif_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/saif_tests/t_trace_ascendingrange_saif_sc.py b/test_regress/t/saif_tests/t_trace_ascendingrange_saif_sc.py deleted file mode 100755 index 7d97731da..000000000 --- a/test_regress/t/saif_tests/t_trace_ascendingrange_saif_sc.py +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') -test.top_filename = "t/t_trace_ascendingrange.v" - -if not test.have_sc: - test.skip("No SystemC installed") - -# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. -# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. -# Strangely, asking for more threads makes it go away. -test.compile(verilator_flags2=['--sc --trace-saif --trace-params -Wno-ASCRANGE'], - threads=(6 if test.vltmt else 1)) - -test.execute() - -test.saif_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/saif_tests/t_trace_cat_saif.py b/test_regress/t/saif_tests/t_trace_cat_saif.py deleted file mode 100755 index 556b800a8..000000000 --- a/test_regress/t/saif_tests/t_trace_cat_saif.py +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt_all') - -test.top_filename = "t/t_trace_cat_fst.v" - -test.compile(make_top_shell=False, - make_main=False, - v_flags2=["--trace-saif --exe", test.pli_filename]) - -test.execute() - -test.saif_identical(test.obj_dir + "/simpart_0000.saif", "t/" + test.name + "_0000.saif") -test.saif_identical(test.obj_dir + "/simpart_0100.saif", "t/" + test.name + "_0100.saif") - -test.passes() diff --git a/test_regress/t/saif_tests/t_trace_complex_params_saif.py b/test_regress/t/saif_tests/t_trace_complex_params_saif.py deleted file mode 100755 index f31d18818..000000000 --- a/test_regress/t/saif_tests/t_trace_complex_params_saif.py +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') -test.top_filename = "t/t_trace_complex.v" - -test.compile(verilator_flags2=['--cc --trace-saif --no-trace-structs --trace-params']) - -test.execute() - -test.saif_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/saif_tests/t_trace_complex_params_saif_sc.py b/test_regress/t/saif_tests/t_trace_complex_params_saif_sc.py deleted file mode 100755 index 0510d838f..000000000 --- a/test_regress/t/saif_tests/t_trace_complex_params_saif_sc.py +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') -test.top_filename = "t/t_trace_complex.v" - -if not test.have_sc: - test.skip("No SystemC installed") - -test.compile(verilator_flags2=['--sc --trace-saif --no-trace-structs --trace-params']) - -test.execute() - -test.saif_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/saif_tests/t_trace_complex_saif.py b/test_regress/t/saif_tests/t_trace_complex_saif.py deleted file mode 100755 index c3bc9d4c2..000000000 --- a/test_regress/t/saif_tests/t_trace_complex_saif.py +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') -test.top_filename = "t/t_trace_complex.v" - -test.compile(verilator_flags2=['--cc --trace-saif']) - -test.execute() - -test.saif_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/saif_tests/t_trace_complex_saif_sc.py b/test_regress/t/saif_tests/t_trace_complex_saif_sc.py deleted file mode 100755 index 268690520..000000000 --- a/test_regress/t/saif_tests/t_trace_complex_saif_sc.py +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') -test.top_filename = "t/t_trace_complex.v" - -if not test.have_sc: - test.skip("No SystemC installed") - -test.compile(verilator_flags2=['--sc --trace-saif']) - -test.execute() - -test.saif_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/saif_tests/t_trace_complex_saif_threads_1.py b/test_regress/t/saif_tests/t_trace_complex_saif_threads_1.py deleted file mode 100755 index 2d0d7fd70..000000000 --- a/test_regress/t/saif_tests/t_trace_complex_saif_threads_1.py +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') -test.top_filename = "t/t_trace_complex.v" -test.golden_filename = "t/t_trace_complex_fst.out" - -test.compile(verilator_flags2=['--cc --trace-saif --trace-threads 1']) - -test.execute() - -test.saif_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/saif_tests/t_trace_complex_saif_threads_1_sc.py b/test_regress/t/saif_tests/t_trace_complex_saif_threads_1_sc.py deleted file mode 100755 index ad7343ed0..000000000 --- a/test_regress/t/saif_tests/t_trace_complex_saif_threads_1_sc.py +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') -test.top_filename = "t/t_trace_complex.v" -test.golden_filename = "t/t_trace_complex_fst_sc.out" - -if not test.have_sc: - test.skip("No SystemC installed") - -test.compile(verilator_flags2=['--sc --trace-saif --trace-threads 1']) - -test.execute() - -test.saif_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/saif_tests/t_trace_complex_saif_threads_2.py b/test_regress/t/saif_tests/t_trace_complex_saif_threads_2.py deleted file mode 100755 index 1eb64d6d8..000000000 --- a/test_regress/t/saif_tests/t_trace_complex_saif_threads_2.py +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') -test.top_filename = "t/t_trace_complex.v" -test.golden_filename = "t/t_trace_complex_fst.out" - -test.compile(verilator_flags2=['--cc --trace-saif --trace-threads 2']) - -test.execute() - -test.saif_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/saif_tests/t_trace_complex_saif_threads_2_sc.py b/test_regress/t/saif_tests/t_trace_complex_saif_threads_2_sc.py deleted file mode 100755 index 5ede01f0a..000000000 --- a/test_regress/t/saif_tests/t_trace_complex_saif_threads_2_sc.py +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') -test.top_filename = "t/t_trace_complex.v" -test.golden_filename = "t/t_trace_complex_fst_sc.out" - -if not test.have_sc: - test.skip("No SystemC installed") - -test.compile(verilator_flags2=['--sc --trace-saif --trace-threads 2']) - -test.execute() - -test.saif_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/saif_tests/t_trace_complex_structs_saif.py b/test_regress/t/saif_tests/t_trace_complex_structs_saif.py deleted file mode 100755 index 2a2b74369..000000000 --- a/test_regress/t/saif_tests/t_trace_complex_structs_saif.py +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') -test.top_filename = "t/t_trace_complex.v" - -test.compile(verilator_flags2=['--cc --trace-saif --trace-structs --no-trace-params']) - -test.execute() - -test.saif_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/saif_tests/t_trace_complex_structs_saif_sc.py b/test_regress/t/saif_tests/t_trace_complex_structs_saif_sc.py deleted file mode 100755 index c51d5ba80..000000000 --- a/test_regress/t/saif_tests/t_trace_complex_structs_saif_sc.py +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') -test.top_filename = "t/t_trace_complex.v" - -if not test.have_sc: - test.skip("No SystemC installed") - -test.compile(verilator_flags2=['--sc --trace-saif --trace-structs --no-trace-params']) - -test.execute() - -test.saif_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/saif_tests/t_trace_counter_saif.py b/test_regress/t/saif_tests/t_trace_counter_saif.py deleted file mode 100755 index 0873571c9..000000000 --- a/test_regress/t/saif_tests/t_trace_counter_saif.py +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test module -# -# Copyright 2025 by Antmicro. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt') -test.top_filename = "t/t_trace_counter.v" - -test.compile(verilator_flags2=['--cc --trace']) - -test.execute() - -#TODO: add function checking if two SAIF files are identical -#test.saif_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/saif_tests/t_trace_dumpvars_dyn_saif_0.py b/test_regress/t/saif_tests/t_trace_dumpvars_dyn_saif_0.py deleted file mode 100755 index 44835a822..000000000 --- a/test_regress/t/saif_tests/t_trace_dumpvars_dyn_saif_0.py +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt_all') -test.pli_filename = "t/t_trace_dumpvars_dyn.cpp" -test.top_filename = "t/t_trace_dumpvars_dyn.v" - -test.compile(make_main=False, verilator_flags2=["--trace-saif --exe", test.pli_filename]) - -test.execute() - -test.saif_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/saif_tests/t_trace_dumpvars_dyn_saif_1.py b/test_regress/t/saif_tests/t_trace_dumpvars_dyn_saif_1.py deleted file mode 100755 index 44835a822..000000000 --- a/test_regress/t/saif_tests/t_trace_dumpvars_dyn_saif_1.py +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt_all') -test.pli_filename = "t/t_trace_dumpvars_dyn.cpp" -test.top_filename = "t/t_trace_dumpvars_dyn.v" - -test.compile(make_main=False, verilator_flags2=["--trace-saif --exe", test.pli_filename]) - -test.execute() - -test.saif_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/saif_tests/t_trace_enum_saif.py b/test_regress/t/saif_tests/t_trace_enum_saif.py deleted file mode 100755 index 7f689fbdb..000000000 --- a/test_regress/t/saif_tests/t_trace_enum_saif.py +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') -test.top_filename = "t/t_trace_enum.v" - -test.compile(verilator_flags2=['--cc --trace-saif --output-split-ctrace 1']) - -test.execute() - -test.saif_identical(test.trace_filename, test.golden_filename) - -# Five $attrbegin expected: -# - state_t declaration -# - t.v_enumed -# - t.sink.state -# - other_state_t declaration -# - t.v_other_enumed -test.file_grep_count(test.golden_filename, r'attrbegin', 5) - -test.passes() diff --git a/test_regress/t/saif_tests/t_trace_jumps_do_while_saif.py b/test_regress/t/saif_tests/t_trace_jumps_do_while_saif.py deleted file mode 100755 index 82bf14639..000000000 --- a/test_regress/t/saif_tests/t_trace_jumps_do_while_saif.py +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test module -# -# Copyright 2025 by Antmicro. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt') -test.top_filename = "t/t_jumps_do_while.v" - -test.compile(verilator_flags2=['--trace-saif']) - -test.execute() - -#TODO: add function checking if two SAIF files are identical -#test.saif_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/saif_tests/t_trace_no_top_name2_saif.py b/test_regress/t/saif_tests/t_trace_no_top_name2_saif.py deleted file mode 100755 index 5035c849b..000000000 --- a/test_regress/t/saif_tests/t_trace_no_top_name2_saif.py +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt') -test.pli_filename = "t/t_trace_no_top_name2.cpp" -test.top_filename = "t/t_trace_no_top_name2.v" - -test.compile(make_main=False, verilator_flags2=["--trace-saif --exe", test.pli_filename]) - -test.execute() - -test.saif_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/saif_tests/t_trace_packed_struct_saif.py b/test_regress/t/saif_tests/t_trace_packed_struct_saif.py deleted file mode 100755 index 60986d596..000000000 --- a/test_regress/t/saif_tests/t_trace_packed_struct_saif.py +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') -test.top_filename = "t/t_trace_packed_struct.v" - -test.compile(v_flags2=["--trace-saif"]) - -test.execute() - -test.saif_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/saif_tests/t_trace_packed_struct_saif_sc.py b/test_regress/t/saif_tests/t_trace_packed_struct_saif_sc.py deleted file mode 100755 index d7c819ef6..000000000 --- a/test_regress/t/saif_tests/t_trace_packed_struct_saif_sc.py +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') -test.top_filename = "t/t_trace_packed_struct.v" - -if not test.have_sc: - test.skip("No SystemC installed") - -test.compile(v_flags2=["--sc --trace-saif"]) - -test.execute() - -test.saif_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/saif_tests/t_trace_param_saif.py b/test_regress/t/saif_tests/t_trace_param_saif.py deleted file mode 100755 index 981062c76..000000000 --- a/test_regress/t/saif_tests/t_trace_param_saif.py +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt_all') -test.top_filename = "t/t_trace_param.v" - -test.compile(v_flags2=["--trace-saif"]) - -test.execute() - -test.passes() diff --git a/test_regress/t/saif_tests/t_trace_primitive_saif.py b/test_regress/t/saif_tests/t_trace_primitive_saif.py deleted file mode 100755 index 65acc5dd6..000000000 --- a/test_regress/t/saif_tests/t_trace_primitive_saif.py +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') -test.top_filename = "t/t_trace_primitive.v" - -test.compile(v_flags2=["--trace-saif"]) - -test.execute() - -test.passes() diff --git a/test_regress/t/saif_tests/t_trace_primitive_saif_sc.py b/test_regress/t/saif_tests/t_trace_primitive_saif_sc.py deleted file mode 100755 index 04e646311..000000000 --- a/test_regress/t/saif_tests/t_trace_primitive_saif_sc.py +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') -test.top_filename = "t/t_trace_primitive.v" - -if not test.have_sc: - test.skip("No SystemC installed") - -test.compile(v_flags2=["--sc --trace-saif"]) - -test.execute() - -test.passes() diff --git a/test_regress/t/saif_tests/t_trace_saif.py b/test_regress/t/saif_tests/t_trace_saif.py deleted file mode 100755 index ec0b35e75..000000000 --- a/test_regress/t/saif_tests/t_trace_saif.py +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt_all') - -test.compile(v_flags2=["--trace-saif"]) - -test.execute() - -test.saif_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/saif_tests/t_trace_saif.v b/test_regress/t/saif_tests/t_trace_saif.v deleted file mode 100644 index 288ddadfc..000000000 --- a/test_regress/t/saif_tests/t_trace_saif.v +++ /dev/null @@ -1,99 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed into the Public Domain, for any use, -// Author: Yu-Sheng Lin johnjohnlys@media.ee.ntu.edu.tw -// SPDX-License-Identifier: CC0-1.0 - -module t (/*AUTOARG*/ - // Outputs - state, - // Inputs - clk - ); - - input clk; - - int cyc; - reg rstn; - output [4:0] state; - - parameter real fst_gparam_real = 1.23; - localparam real fst_lparam_real = 4.56; - real fst_real = 1.23; - integer fst_integer; - bit fst_bit; - logic fst_logic; - int fst_int; - shortint fst_shortint; - longint fst_longint; - byte fst_byte; - - parameter fst_parameter = 123; - localparam fst_lparam = 456; - supply0 fst_supply0; - supply1 fst_supply1; - tri0 fst_tri0; - tri1 fst_tri1; - tri fst_tri; - wire fst_wire; - - Test test (/*AUTOINST*/ - // Outputs - .state (state[4:0]), - // Inputs - .clk (clk), - .rstn (rstn)); - - // Test loop - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc==0) begin - // Setup - rstn <= ~'1; - end - else if (cyc<10) begin - rstn <= ~'1; - end - else if (cyc<90) begin - rstn <= ~'0; - end - else if (cyc==99) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - -endmodule - - -module Test ( - input clk, - input rstn, - output logic [4:0] state - ); - - logic [4:0] state_w; - logic [4:0] state_array [3]; - assign state = state_array[0]; - - always_comb begin - state_w[4] = state_array[2][0]; - state_w[3] = state_array[2][4]; - state_w[2] = state_array[2][3] ^ state_array[2][0]; - state_w[1] = state_array[2][2]; - state_w[0] = state_array[2][1]; - end - - always_ff @(posedge clk or negedge rstn) begin - if (!rstn) begin - for (int i = 0; i < 3; i++) - state_array[i] <= 'b1; - end - else begin - for (int i = 0; i < 2; i++) - state_array[i] <= state_array[i+1]; - state_array[2] <= state_w; - end - end - -endmodule diff --git a/test_regress/t/saif_tests/t_trace_saif_sc.py b/test_regress/t/saif_tests/t_trace_saif_sc.py deleted file mode 100755 index d8ff6413a..000000000 --- a/test_regress/t/saif_tests/t_trace_saif_sc.py +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt_all') - -if not test.have_sc: - test.skip("No SystemC installed") - -test.compile(verilator_flags2=["--trace-saif --sc"]) - -test.execute() - -test.saif_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/saif_tests/t_trace_saif_sc_cmake.py b/test_regress/t/saif_tests/t_trace_saif_sc_cmake.py deleted file mode 100755 index 50d89cb33..000000000 --- a/test_regress/t/saif_tests/t_trace_saif_sc_cmake.py +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt_all') - -if not test.have_sc: - test.skip("No SystemC installed") - -test.compile(verilator_flags2=["--trace-saif --sc"], - verilator_make_gmake=False, - verilator_make_cmake=1) - -test.execute() - -test.saif_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/saif_tests/t_trace_string_saif.py b/test_regress/t/saif_tests/t_trace_string_saif.py index cf926f0d2..38c5aa5db 100755 --- a/test_regress/t/saif_tests/t_trace_string_saif.py +++ b/test_regress/t/saif_tests/t_trace_string_saif.py @@ -12,7 +12,7 @@ import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_trace_string.v" -test.compile(verilator_flags2=['--cc --trace']) +test.compile(verilator_flags2=['--cc --trace-saif']) test.execute() diff --git a/test_regress/t/saif_tests/t_trace_string_saif_sc.py b/test_regress/t/saif_tests/t_trace_string_saif_sc.py deleted file mode 100755 index dc56e4069..000000000 --- a/test_regress/t/saif_tests/t_trace_string_saif_sc.py +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') -test.top_filename = "t/t_trace_string.v" - -if not test.have_sc: - test.skip("No SystemC installed") - -test.compile(verilator_flags2=['--sc --trace']) - -test.execute() - -test.passes()