mirror of
https://github.com/verilator/verilator.git
synced 2026-10-06 10:03:44 +02:00
@@ -414,3 +414,38 @@ void V3LinkLevel::wrapTopCell(AstNetlist* rootp) {
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}
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}
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}
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void V3LinkLevel::nonWrapTop(AstNetlist* rootp) {
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// Perform variable setting step for top modules to prevent
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// optimizing away primary ports when only serializing input
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if (!rootp->modulesp()) { // Later V3LinkDot will warn
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UINFO(1, "No module found");
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return;
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}
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// For all top modules
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for (AstNodeModule* modp = rootp->modulesp(); modp && modp->isTop();
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modp = VN_AS(modp->nextp(), NodeModule)) {
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if (VN_IS(modp, Package)) continue;
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UINFO(5, "LOOP " << modp);
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for (AstNode* subnodep = modp->stmtsp(); subnodep; subnodep = subnodep->nextp()) {
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if (AstVar* const varp = VN_CAST(subnodep, Var)) {
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UINFO(8, "VARWRAP " << varp);
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if (varp->isIO()) {
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varp->protect(false);
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varp->sigPublic(true);
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varp->primaryIO(true);
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if (varp->isRef() || varp->isConstRef()) {
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varp->v3warn(E_UNSUPPORTED,
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"Unsupported: ref/const ref as primary input/output: "
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<< varp->prettyNameQ());
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}
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if (v3Global.opt.systemC()) varp->sc(true);
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if (v3Global.opt.noTraceTop()) varp->trace(false);
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}
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}
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}
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}
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}
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