Introduction of a regression test

Signed-off-by: Igor Zaworski <izaworski@internships.antmicro.com>
This commit is contained in:
Igor Zaworski 2026-01-20 13:16:50 +01:00
parent 03024f3cef
commit a07839e9e0
2 changed files with 60 additions and 0 deletions

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#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2026 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.compile()
test.execute()
test.passes()

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// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2026 by Antmicro.
// SPDX-License-Identifier: CC0-1.0
class Base;
int k = 3;
function new(int x);
k = x;
endfunction
protected function int get_x_base();
Base f = this;
return 7;
endfunction
endclass
class Foo extends Base;
function new(int x);
super.new(x);
endfunction
protected function int get_x();
Foo f = this;
return get_x_base();
endfunction
endclass
class Bar extends Foo;
function new();
super.new(get_x());
endfunction
endclass
module top;
initial begin
static Bar b = new();
if (b.k != 7) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule