Introduction of a regression test
Signed-off-by: Igor Zaworski <izaworski@internships.antmicro.com>
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2026 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.compile()
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test.execute()
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test.passes()
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2026 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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class Base;
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int k = 3;
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function new(int x);
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k = x;
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endfunction
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protected function int get_x_base();
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Base f = this;
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return 7;
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endfunction
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endclass
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class Foo extends Base;
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function new(int x);
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super.new(x);
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endfunction
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protected function int get_x();
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Foo f = this;
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return get_x_base();
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endfunction
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endclass
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class Bar extends Foo;
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function new();
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super.new(get_x());
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endfunction
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endclass
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module top;
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initial begin
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static Bar b = new();
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if (b.k != 7) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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