diff --git a/test_regress/t/t_class_new_base_call.py b/test_regress/t/t_class_new_base_call.py
new file mode 100755
index 000000000..e41ab0cdd
--- /dev/null
+++ b/test_regress/t/t_class_new_base_call.py
@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2026 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile()
+
+test.execute()
+
+test.passes()
diff --git a/test_regress/t/t_class_new_base_call.v b/test_regress/t/t_class_new_base_call.v
new file mode 100644
index 000000000..fcb6d3f4a
--- /dev/null
+++ b/test_regress/t/t_class_new_base_call.v
@@ -0,0 +1,42 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2026 by Antmicro.
+// SPDX-License-Identifier: CC0-1.0
+
+class Base;
+  int k = 3;
+  function new(int x);
+    k = x;
+  endfunction
+  protected function int get_x_base();
+    Base f = this;
+    return 7;
+  endfunction
+endclass
+
+class Foo extends Base;
+  function new(int x);
+    super.new(x);
+  endfunction
+
+  protected function int get_x();
+    Foo f = this;
+    return get_x_base();
+  endfunction
+endclass
+
+class Bar extends Foo;
+  function new();
+    super.new(get_x());
+  endfunction
+endclass
+
+module top;
+  initial begin
+    static Bar b = new();
+    if (b.k != 7) $stop;
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
+endmodule