Fix segfault on SystemVerilog "output wire foo=0", bug291.

Changes

@@ -7,6 +7,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 **** Fix wrong filename on include file errors, bug289. [Brad Parker]
 
+**** Fix segfault on SystemVerilog "output wire foo=0", bug291.  [Joshua Wise]
+
 * Verilator 3.804 2010/09/20
 
 ***  Support tracing/coverage of underscore signals, bug280.  [by Jason McMullan]

src/verilog.y

@@ -826,11 +826,11 @@ port<nodep>:			// ==IEEE: port
 	|	portDirNetE data_type           portSig variable_dimensionListE sigAttrListE '=' constExpr
 			{ $$=$3; VARDTYPE($2); AstVar* vp=VARDONEP($$,$4,$5); $$->addNextNull(vp); vp->valuep($7); }
 	|	portDirNetE yVAR data_type      portSig variable_dimensionListE sigAttrListE '=' constExpr
-			{ $$=$3; VARDTYPE($3); AstVar* vp=VARDONEP($$,$5,$6); $$->addNextNull(vp); vp->valuep($8); }
+			{ $$=$4; VARDTYPE($3); AstVar* vp=VARDONEP($$,$5,$6); $$->addNextNull(vp); vp->valuep($8); }
 	|	portDirNetE yVAR implicit_typeE portSig variable_dimensionListE sigAttrListE '=' constExpr
-			{ $$=$3; VARDTYPE($3); AstVar* vp=VARDONEP($$,$5,$6); $$->addNextNull(vp); vp->valuep($8); }
+			{ $$=$4; VARDTYPE($3); AstVar* vp=VARDONEP($$,$5,$6); $$->addNextNull(vp); vp->valuep($8); }
 	|	portDirNetE /*implicit*/        portSig variable_dimensionListE sigAttrListE '=' constExpr
-			{ $$=$3; /*VARDTYPE-same*/ AstVar* vp=VARDONEP($$,$3,$4); $$->addNextNull(vp); vp->valuep($6); }
+			{ $$=$2; /*VARDTYPE-same*/ AstVar* vp=VARDONEP($$,$3,$4); $$->addNextNull(vp); vp->valuep($6); }
  	;
  
 portDirNetE:			// IEEE: part of port, optional net type and/or direction

test_regress/t/t_var_tieout.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+	 );
+
+execute (
+	 check_finished=>1,
+     );
+
+ok(1);
+1;

test_regress/t/t_var_tieout.v

@@ -0,0 +1,45 @@
+// DESCRIPTION: Verilator: Verilog Test module
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2010 by Wilson Snyder.
+
+// bug291 
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   integer  out18;
+   /*AUTOWIRE*/
+   // Beginning of automatic wires (for undeclared instantiated-module outputs)
+   wire			out1;			// From test of Test.v
+   wire			out19;			// From test of Test.v
+   wire			out1b;			// From test of Test.v
+   // End of automatics
+
+   Test test (/*AUTOINST*/
+	      // Outputs
+	      .out1			(out1),
+	      .out18			(out18),
+	      .out1b			(out1b),
+	      .out19			(out19));
+
+   // Test loop
+   always @ (posedge clk) begin
+      if (out1 !== 1'b1) $stop;
+      if (out18 !== 32'h18) $stop;
+      if (out1b !== 1'b1) $stop;
+      if (out19 !== 1'b1) $stop;
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule
+
+module Test (
+	     output wire out1 = 1'b1,
+	     output integer out18 = 32'h18,
+	     output var out1b = 1'b1,
+	     output var logic out19 = 1'b1
+	     );
+endmodule