Fix of deleting linked node in V3Randomize (#6718)
Signed-off-by: Igor Zaworski <izaworski@internships.antmicro.com>
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@ -900,7 +900,7 @@ class ConstraintExprVisitor final : public VNVisitor {
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// Track this variable path as written
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// Track this variable path as written
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if (isGlobalConstrained) m_writtenVars.insert(smtName);
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if (isGlobalConstrained) m_writtenVars.insert(smtName);
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// For global constraints, delete nodep after processing
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// For global constraints, delete nodep after processing
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if (isGlobalConstrained) VL_DO_DANGLING(pushDeletep(nodep), nodep);
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if (isGlobalConstrained && !nodep->backp()) VL_DO_DANGLING(pushDeletep(nodep), nodep);
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AstCMethodHard* const methodp = new AstCMethodHard{
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AstCMethodHard* const methodp = new AstCMethodHard{
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varp->fileline(),
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varp->fileline(),
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new AstVarRef{varp->fileline(), VN_AS(m_genp->user2p(), NodeModule), m_genp,
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new AstVarRef{varp->fileline(), VN_AS(m_genp->user2p(), NodeModule), m_genp,
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@ -958,7 +958,7 @@ class ConstraintExprVisitor final : public VNVisitor {
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// Variable already written, clean up cloned membersel if any
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// Variable already written, clean up cloned membersel if any
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if (membersel) VL_DO_DANGLING(membersel->deleteTree(), membersel);
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if (membersel) VL_DO_DANGLING(membersel->deleteTree(), membersel);
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// Delete nodep if it's a global constraint (not deleted yet)
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// Delete nodep if it's a global constraint (not deleted yet)
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if (isGlobalConstrained) VL_DO_DANGLING(pushDeletep(nodep), nodep);
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if (isGlobalConstrained && !nodep->backp()) VL_DO_DANGLING(pushDeletep(nodep), nodep);
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}
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}
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}
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}
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void visit(AstCountOnes* nodep) override {
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void visit(AstCountOnes* nodep) override {
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@ -0,0 +1,18 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2025 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.compile()
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test.execute()
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test.passes()
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@ -0,0 +1,36 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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class RandomValue;
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rand int value;
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constraint small_int_c {
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value < 10;
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}
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task disable_val();
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value.rand_mode(0);
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endtask
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endclass
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class Base;
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endclass
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class Foo extends Base;
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rand RandomValue v = new;
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endclass
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module t;
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Base b;
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initial begin
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Foo d = new;
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b = d;
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d.v.disable_val();
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d.v.value = 11;
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if (bit'(b.randomize())) $stop;
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if (d.v.value != 11) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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