diff --git a/src/V3Randomize.cpp b/src/V3Randomize.cpp
index 7caaaba7f..6ee477439 100644
--- a/src/V3Randomize.cpp
+++ b/src/V3Randomize.cpp
@@ -900,7 +900,7 @@ class ConstraintExprVisitor final : public VNVisitor {
             // Track this variable path as written
             if (isGlobalConstrained) m_writtenVars.insert(smtName);
             // For global constraints, delete nodep after processing
-            if (isGlobalConstrained) VL_DO_DANGLING(pushDeletep(nodep), nodep);
+            if (isGlobalConstrained && !nodep->backp()) VL_DO_DANGLING(pushDeletep(nodep), nodep);
             AstCMethodHard* const methodp = new AstCMethodHard{
                 varp->fileline(),
                 new AstVarRef{varp->fileline(), VN_AS(m_genp->user2p(), NodeModule), m_genp,
@@ -958,7 +958,7 @@ class ConstraintExprVisitor final : public VNVisitor {
             // Variable already written, clean up cloned membersel if any
             if (membersel) VL_DO_DANGLING(membersel->deleteTree(), membersel);
             // Delete nodep if it's a global constraint (not deleted yet)
-            if (isGlobalConstrained) VL_DO_DANGLING(pushDeletep(nodep), nodep);
+            if (isGlobalConstrained && !nodep->backp()) VL_DO_DANGLING(pushDeletep(nodep), nodep);
         }
     }
     void visit(AstCountOnes* nodep) override {
diff --git a/test_regress/t/t_rand_member_mode_deriv.py b/test_regress/t/t_rand_member_mode_deriv.py
new file mode 100755
index 000000000..f989a35fb
--- /dev/null
+++ b/test_regress/t/t_rand_member_mode_deriv.py
@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile()
+
+test.execute()
+
+test.passes()
diff --git a/test_regress/t/t_rand_member_mode_deriv.v b/test_regress/t/t_rand_member_mode_deriv.v
new file mode 100644
index 000000000..00a4924ba
--- /dev/null
+++ b/test_regress/t/t_rand_member_mode_deriv.v
@@ -0,0 +1,36 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Antmicro.
+// SPDX-License-Identifier: CC0-1.0
+
+class RandomValue;
+  rand int value;
+  constraint small_int_c {
+    value < 10;
+  }
+  task disable_val();
+    value.rand_mode(0);
+  endtask
+endclass
+
+class Base;
+endclass
+
+class Foo extends Base;
+  rand RandomValue v = new;
+endclass
+
+module t;
+  Base b;
+  initial begin
+    Foo d = new;
+    b = d;
+    d.v.disable_val();
+    d.v.value = 11;
+    if (bit'(b.randomize())) $stop;
+    if (d.v.value != 11) $stop;
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
+endmodule