51 lines
1.1 KiB
Systemverilog
Executable File
51 lines
1.1 KiB
Systemverilog
Executable File
// DESCRIPTION: Verilator: Verilog Test module
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//
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// Simple test for unpacked concatenation arrays used as function arguments.
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2026 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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//
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class A;
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int r1[2];
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int r2;
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endclass
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class B;
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virtual function int B_virt_func(int r[3], p[4]);
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return r[0] + r[1] + r[2] + p[0] + p[1] + p[2] + p[3];
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endfunction
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endclass
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function int func_1_concat(int r[4]);
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// verilator no_inline_task
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return r[0] + r[1] + r[2] + r[3];
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endfunction
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function int func_2_concat(int r[3], int p[4]);
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// verilator no_inline_task
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return r[0] + r[1] + r[2] + p[0] + p[1] + p[2] + p[3];
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endfunction
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module t;
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int s;
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A a = new;
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B b = new;
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initial begin
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a.r1 = {1, 2};
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a.r2 = 5;
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s = func_1_concat({a.r1, a.r1});
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if (s != 6) $stop;
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s = func_2_concat({a.r1, a.r2}, {a.r1, a.r1});
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if (s != 14) $stop;
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s = b.B_virt_func({a.r1, a.r2}, {a.r1, a.r1});
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if (s != 14) $stop;
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$write("*-* All finished *-*\n");
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$finish;
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end
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endmodule
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