Warnings: Suppress dup lines, and use lowercase note: to match gcc

src/V3Error.cpp

@@ -177,9 +177,15 @@ void V3Error::v3errorEnd(std::ostringstream& sstr) {
             msg += "...";
         }
     }
-    // Trailing newline
-    if (msg[msg.length()-1] != '\n') msg += '\n';
-    // Suppress duplicates
+    // Trailing newline (generally not on messages) & remove dup newlines
+    {
+        msg += '\n';  // Trailing newlines generally not put on messages so add
+        string::size_type pos;
+        while ((pos = msg.find("\n\n")) != string::npos) {
+            msg.erase(pos+1, 1);
+        }
+    }
+    // Suppress duplicate messages
     if (s_messages.find(msg) != s_messages.end()) return;
     s_messages.insert(msg);
     // Output

src/V3LinkCells.cpp

@@ -81,7 +81,7 @@ void LinkCellsGraph::loopsMessageCb(V3GraphVertex* vertexp) {
         vvertexp->modp()->v3error("Unsupported: Recursive multiple modules (module instantiates something leading back to itself): "
                                   <<vvertexp->modp()->prettyName()<<endl
                                   <<V3Error::warnMore()
-                                  <<"... Note self-recursion (module instantiating itself directly) is supported.");
+                                  <<"... note: self-recursion (module instantiating itself directly) is supported.");
         V3Error::abortIfErrors();
     } else {  // Everything should match above, but...
         v3fatalSrc("Recursive instantiations");

src/V3LinkDot.cpp

@@ -942,10 +942,10 @@ class LinkDotFindVisitor : public AstNVisitor {
                         if (ansiWarn) { if (didAnsiWarn++) ansiWarn = false; }
                         nodep->v3error("Duplicate declaration of signal: "
                                        <<nodep->prettyName()<<endl
-                                       <<findvarp->warnMore()<<"... Location of original declaration"<<endl
                                        <<(ansiWarn
-                                          ? findvarp->warnMore()+"... Note: ANSI ports must have type declared with the I/O (IEEE 2017 23.2.2.2)"
-                                          : ""));
+                                          ? findvarp->warnMore()+"... note: ANSI ports must have type declared with the I/O (IEEE 2017 23.2.2.2)\n"
+                                          : "")
+                                       <<findvarp->warnMore()<<"... Location of original declaration");
                         // Combining most likely reduce other errors
                         findvarp->combineType(nodep);
                         findvarp->fileline()->modifyStateInherit(nodep->fileline());

src/verilog.y

@@ -218,7 +218,7 @@ static void ERRSVKWD(FileLine* fileline, const string& tokname) {
                       +"\" is a SystemVerilog keyword misused as an identifier."
                       +(!toldonce++
                         ? "\n"+V3Error::warnMore()
-                          +"... Modify the Verilog-2001 code to avoid SV keywords,"
+                          +"... Suggest modify the Verilog-2001 code to avoid SV keywords,"
                           +" or use `begin_keywords or --language."
                         : ""));
 }

test_regress/t/t_inst_recurse_bad.out

@@ -1,3 +1,3 @@
 %Error: t/t_inst_recurse_bad.v:17: Unsupported: Recursive multiple modules (module instantiates something leading back to itself): looped
-        ... Note self-recursion (module instantiating itself directly) is supported.
+        ... note: self-recursion (module instantiating itself directly) is supported.
 %Error: Exiting due to

test_regress/t/t_var_bad_sv.out

@@ -1,5 +1,5 @@
 %Error: t/t_var_bad_sv.v:7: Unexpected "do": "do" is a SystemVerilog keyword misused as an identifier.
-        ... Modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.
+        ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.
 %Error: t/t_var_bad_sv.v:8: Unexpected "do": "do" is a SystemVerilog keyword misused as an identifier.
 %Error: t/t_var_bad_sv.v:8: syntax error, unexpected '(', expecting ')'
 %Error: Exiting due to

test_regress/t/t_var_dup2_bad.out

@@ -1,6 +1,6 @@
 %Error: t/t_var_dup2_bad.v:12: Duplicate declaration of signal: bad_o_w
+        t/t_var_dup2_bad.v:9: ... note: ANSI ports must have type declared with the I/O (IEEE 2017 23.2.2.2)
         t/t_var_dup2_bad.v:9: ... Location of original declaration
-        t/t_var_dup2_bad.v:9: ... Note: ANSI ports must have type declared with the I/O (IEEE 2017 23.2.2.2)
 %Error: t/t_var_dup2_bad.v:13: Duplicate declaration of signal: bad_o_r
         t/t_var_dup2_bad.v:10: ... Location of original declaration
 %Error: Exiting due to