From 951521320ae8d543d64a48bd9b05d39d65f60176 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sat, 22 Jun 2019 16:09:10 -0400 Subject: [PATCH] Warnings: Suppress dup lines, and use lowercase note: to match gcc --- src/V3Error.cpp | 12 +++++++++--- src/V3LinkCells.cpp | 2 +- src/V3LinkDot.cpp | 6 +++--- src/verilog.y | 2 +- test_regress/t/t_inst_recurse_bad.out | 2 +- test_regress/t/t_var_bad_sv.out | 2 +- test_regress/t/t_var_dup2_bad.out | 2 +- 7 files changed, 17 insertions(+), 11 deletions(-) diff --git a/src/V3Error.cpp b/src/V3Error.cpp index 948908256..42e6f5ede 100644 --- a/src/V3Error.cpp +++ b/src/V3Error.cpp @@ -177,9 +177,15 @@ void V3Error::v3errorEnd(std::ostringstream& sstr) { msg += "..."; } } - // Trailing newline - if (msg[msg.length()-1] != '\n') msg += '\n'; - // Suppress duplicates + // Trailing newline (generally not on messages) & remove dup newlines + { + msg += '\n'; // Trailing newlines generally not put on messages so add + string::size_type pos; + while ((pos = msg.find("\n\n")) != string::npos) { + msg.erase(pos+1, 1); + } + } + // Suppress duplicate messages if (s_messages.find(msg) != s_messages.end()) return; s_messages.insert(msg); // Output diff --git a/src/V3LinkCells.cpp b/src/V3LinkCells.cpp index 8f2cf97a7..1a83f3116 100644 --- a/src/V3LinkCells.cpp +++ b/src/V3LinkCells.cpp @@ -81,7 +81,7 @@ void LinkCellsGraph::loopsMessageCb(V3GraphVertex* vertexp) { vvertexp->modp()->v3error("Unsupported: Recursive multiple modules (module instantiates something leading back to itself): " <modp()->prettyName()<v3error("Duplicate declaration of signal: " <prettyName()<warnMore()<<"... Location of original declaration"<warnMore()+"... Note: ANSI ports must have type declared with the I/O (IEEE 2017 23.2.2.2)" - : "")); + ? findvarp->warnMore()+"... note: ANSI ports must have type declared with the I/O (IEEE 2017 23.2.2.2)\n" + : "") + <warnMore()<<"... Location of original declaration"); // Combining most likely reduce other errors findvarp->combineType(nodep); findvarp->fileline()->modifyStateInherit(nodep->fileline()); diff --git a/src/verilog.y b/src/verilog.y index 953088f68..a5b5d5bf3 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -218,7 +218,7 @@ static void ERRSVKWD(FileLine* fileline, const string& tokname) { +"\" is a SystemVerilog keyword misused as an identifier." +(!toldonce++ ? "\n"+V3Error::warnMore() - +"... Modify the Verilog-2001 code to avoid SV keywords," + +"... Suggest modify the Verilog-2001 code to avoid SV keywords," +" or use `begin_keywords or --language." : "")); } diff --git a/test_regress/t/t_inst_recurse_bad.out b/test_regress/t/t_inst_recurse_bad.out index e25f3952e..c29f68dd9 100644 --- a/test_regress/t/t_inst_recurse_bad.out +++ b/test_regress/t/t_inst_recurse_bad.out @@ -1,3 +1,3 @@ %Error: t/t_inst_recurse_bad.v:17: Unsupported: Recursive multiple modules (module instantiates something leading back to itself): looped - ... Note self-recursion (module instantiating itself directly) is supported. + ... note: self-recursion (module instantiating itself directly) is supported. %Error: Exiting due to diff --git a/test_regress/t/t_var_bad_sv.out b/test_regress/t/t_var_bad_sv.out index 0b64372a4..eec55acb8 100644 --- a/test_regress/t/t_var_bad_sv.out +++ b/test_regress/t/t_var_bad_sv.out @@ -1,5 +1,5 @@ %Error: t/t_var_bad_sv.v:7: Unexpected "do": "do" is a SystemVerilog keyword misused as an identifier. - ... Modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language. + ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language. %Error: t/t_var_bad_sv.v:8: Unexpected "do": "do" is a SystemVerilog keyword misused as an identifier. %Error: t/t_var_bad_sv.v:8: syntax error, unexpected '(', expecting ')' %Error: Exiting due to diff --git a/test_regress/t/t_var_dup2_bad.out b/test_regress/t/t_var_dup2_bad.out index b397c5a11..41679d5f2 100644 --- a/test_regress/t/t_var_dup2_bad.out +++ b/test_regress/t/t_var_dup2_bad.out @@ -1,6 +1,6 @@ %Error: t/t_var_dup2_bad.v:12: Duplicate declaration of signal: bad_o_w + t/t_var_dup2_bad.v:9: ... note: ANSI ports must have type declared with the I/O (IEEE 2017 23.2.2.2) t/t_var_dup2_bad.v:9: ... Location of original declaration - t/t_var_dup2_bad.v:9: ... Note: ANSI ports must have type declared with the I/O (IEEE 2017 23.2.2.2) %Error: t/t_var_dup2_bad.v:13: Duplicate declaration of signal: bad_o_r t/t_var_dup2_bad.v:10: ... Location of original declaration %Error: Exiting due to