From 93531e520a97f7d19789b98864a9558b639478da Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Tue, 25 Mar 2008 19:57:41 +0000 Subject: [PATCH] Add --top-module option to select between multiple tops. [Stefan Thiede] git-svn-id: file://localhost/svn/verilator/trunk/verilator@1010 77ca24e4-aefa-0310-84f0-b9a241c72d87 --- Changes | 2 ++ bin/verilator | 13 ++++++-- src/V3LinkLevel.cpp | 22 +++++++++++-- src/V3Options.cpp | 4 +++ src/V3Options.h | 2 ++ test_regress/t/t_flag_topmodule.pl | 19 +++++++++++ test_regress/t/t_flag_topmodule.v | 32 +++++++++++++++++++ test_regress/t/t_flag_topmodule_bad.pl | 22 +++++++++++++ ...bad_twotop.pl => t_flag_topmodule_bad2.pl} | 10 +++--- test_regress/t/t_mod_bad_twotop.v | 19 ----------- 10 files changed, 118 insertions(+), 27 deletions(-) create mode 100755 test_regress/t/t_flag_topmodule.pl create mode 100644 test_regress/t/t_flag_topmodule.v create mode 100755 test_regress/t/t_flag_topmodule_bad.pl rename test_regress/t/{t_mod_bad_twotop.pl => t_flag_topmodule_bad2.pl} (64%) delete mode 100644 test_regress/t/t_mod_bad_twotop.v diff --git a/Changes b/Changes index 36148b327..956bc9cf3 100644 --- a/Changes +++ b/Changes @@ -7,6 +7,8 @@ indicates the contributor was also the author of the fix; Thanks! **** Fix no-module include files on command line. [Stefan Thiede] +*** Add --top-module option to select between multiple tops. [Stefan Thiede] + * Verilator 3.660 2008/03/23 *** Add support for hard-coding VERILATOR_ROOT etc in the executables, diff --git a/bin/verilator b/bin/verilator index 4a99ca9a8..fbbba3426 100755 --- a/bin/verilator +++ b/bin/verilator @@ -217,6 +217,7 @@ descriptions in the next sections for more information. --sc Create SystemC output --sp Create SystemPerl output --stats Create statistics file + --top-module Name of top level input module --trace Enable waveform creation --trace-depth Depth of tracing -U Undefine preprocessor define @@ -451,8 +452,9 @@ the backward-compatible default of sc_bv's. =item --prefix I -Specifies the name of the top level class. Defaults to the name of the first -Verilog file passed on the command line. +Specifies the name of the top level class and makefile. Defaults to V +prepended to the name of the --top-module switch, or V prepended to the +first Verilog filename passed on the command line. =item --profile-cfuncs @@ -498,6 +500,13 @@ Specifies SystemPerl output mode; see also --cc and -sc. Creates a dump file with statistics on the design in {prefix}__stats.txt. +=item --top-module I + +When the input Verilog contains more than one top level module, specifies +the name of the top level Verilog module to become the top, and sets the +default for if --prefix is not used. This is not needed with standard +designs with only one top. + =item --trace Adds waveform tracing code to the model, this will create additional diff --git a/src/V3LinkLevel.cpp b/src/V3LinkLevel.cpp index e44b0a61d..5701d2061 100644 --- a/src/V3LinkLevel.cpp +++ b/src/V3LinkLevel.cpp @@ -85,6 +85,21 @@ void V3LinkLevel::modSortByLevel() { // Sort modules by levels, root down to lowest children // Calculate levels again in case we added modules UINFO(2,"modSortByLevel()\n"); + + if (v3Global.opt.topModule()!="") { + bool hit = false; + for (AstModule* nodep = v3Global.rootp()->modulesp(); nodep; nodep=nodep->nextp()->castModule()) { + if (nodep->name() == v3Global.opt.topModule()) { + hit = true; + } else { + nodep->level(3); + } + } + if (!hit) { + v3error("Specified --top-module '"<modulesp(); nodep; nodep=nodep->nextp()->castModule()) { if (nodep->level()<=2) { - if (topp) nodep->v3warn(MULTITOP, "Unsupported: Multiple top level modules: " - <prettyName()<<" and "<prettyName()); + if (topp) { + nodep->v3warn(MULTITOP, "Unsupported: Multiple top level modules: " + <prettyName()<<" and "<prettyName()); + nodep->v3warn(MULTITOP, "Fix, or use --top-module option to select which you want."); + } topp = nodep; } vec.push_back(nodep); diff --git a/src/V3Options.cpp b/src/V3Options.cpp index 24867f045..5f30e9cf8 100644 --- a/src/V3Options.cpp +++ b/src/V3Options.cpp @@ -429,6 +429,7 @@ void V3Options::parseOpts (FileLine* fl, int argc, char** argv) { } // Default prefix to the filename + if (prefix()=="") m_prefix = string("V")+topModule(); if (prefix()=="") m_prefix = string("V")+filenameNonExt(*(vFiles().begin())); if (modPrefix()=="") m_modPrefix = prefix(); @@ -654,6 +655,9 @@ void V3Options::parseOptsList(FileLine* fl, int argc, char** argv) { shift; m_prefix = argv[i]; if (m_modPrefix=="") m_modPrefix = m_prefix; } + else if ( !strcmp (sw, "-top-module") && (i+1) ["--top-module b"], + ) if $Last_Self->{v3}; + +execute ( + check_finished=>1, + ) if $Last_Self->{v3}; + +ok(1); +1; diff --git a/test_regress/t/t_flag_topmodule.v b/test_regress/t/t_flag_topmodule.v new file mode 100644 index 000000000..417cfd9a6 --- /dev/null +++ b/test_regress/t/t_flag_topmodule.v @@ -0,0 +1,32 @@ +// $Id$ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Wilson Snyder. + +module a; + c c (); + initial begin + $write("Bad top modules\n"); + $stop; + end +endmodule + +module b; + d d (); +endmodule + +module c; + initial begin + $write("Bad top modules\n"); + $stop; + end +endmodule + +module d; + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule + diff --git a/test_regress/t/t_flag_topmodule_bad.pl b/test_regress/t/t_flag_topmodule_bad.pl new file mode 100755 index 000000000..1a44820aa --- /dev/null +++ b/test_regress/t/t_flag_topmodule_bad.pl @@ -0,0 +1,22 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } +# $Id$ +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2008 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# General Public License or the Perl Artistic License. + +top_filename("t/t_flag_topmodule.v"); + +compile ( + fails=>$Last_Self->{v3}, + nc=>0, # Need to get it not to give the prompt + expect=> +'%Error-MULTITOP: t/t_flag_topmodule.v:\d+: Unsupported: Multiple top level modules: .* +%Error-MULTITOP: t/t_flag_topmodule.v:\d+: Fix, or use --top-module option to select which you want. +%Error: Exiting due to.*', + ) if $Last_Self->{v3}; + +ok(1); +1; diff --git a/test_regress/t/t_mod_bad_twotop.pl b/test_regress/t/t_flag_topmodule_bad2.pl similarity index 64% rename from test_regress/t/t_mod_bad_twotop.pl rename to test_regress/t/t_flag_topmodule_bad2.pl index d5f9d16bf..841e8b0ec 100755 --- a/test_regress/t/t_mod_bad_twotop.pl +++ b/test_regress/t/t_flag_topmodule_bad2.pl @@ -3,18 +3,20 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } # $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can +# Copyright 2008 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # General Public License or the Perl Artistic License. +top_filename("t/t_flag_topmodule.v"); + compile ( fails=>$Last_Self->{v3}, + v_flags2 => ["--top-module notfound"], nc=>0, # Need to get it not to give the prompt expect=> -'%Error-MULTITOP: t/t_mod_bad_twotop.v:\d+: Unsupported: Multiple top level modules: t2 and t +'%Error: Specified --top-module \'notfound\' was not found in design. %Error: Exiting due to.*', - ); + ) if $Last_Self->{v3}; ok(1); 1; - diff --git a/test_regress/t/t_mod_bad_twotop.v b/test_regress/t/t_mod_bad_twotop.v deleted file mode 100644 index 670fb28ec..000000000 --- a/test_regress/t/t_mod_bad_twotop.v +++ /dev/null @@ -1,19 +0,0 @@ -// $Id:$ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. - -module t; - initial begin - $write("Two top modules\n"); - $stop; - end -endmodule - -module t2; - initial begin - $write("Two top modules\n"); - $stop; - end -endmodule