From 8e55fa1f05d39a54fd95c034c3474c1fbc1cec35 Mon Sep 17 00:00:00 2001 From: em2machine <92717390+em2machine@users.noreply.github.com> Date: Wed, 24 Dec 2025 13:57:35 +0100 Subject: [PATCH] coalesced class tests into a single test --- ...riven_class0.py => t_multidriven_class.py} | 0 test_regress/t/t_multidriven_class.v | 284 ++++++++++++++++++ test_regress/t/t_multidriven_class0.v | 72 ----- test_regress/t/t_multidriven_class1.py | 18 -- test_regress/t/t_multidriven_class1.v | 72 ----- test_regress/t/t_multidriven_class2.py | 18 -- test_regress/t/t_multidriven_class2.v | 71 ----- test_regress/t/t_multidriven_class3.py | 18 -- test_regress/t/t_multidriven_class3.v | 66 ---- test_regress/t/t_multidriven_class4.py | 18 -- test_regress/t/t_multidriven_class4.v | 79 ----- test_regress/t/t_multidriven_classf0.py | 18 -- test_regress/t/t_multidriven_classf0.v | 69 ----- test_regress/t/t_multidriven_classf1.py | 18 -- test_regress/t/t_multidriven_classf1.v | 66 ---- 15 files changed, 284 insertions(+), 603 deletions(-) rename test_regress/t/{t_multidriven_class0.py => t_multidriven_class.py} (100%) mode change 100755 => 100644 create mode 100644 test_regress/t/t_multidriven_class.v delete mode 100644 test_regress/t/t_multidriven_class0.v delete mode 100755 test_regress/t/t_multidriven_class1.py delete mode 100644 test_regress/t/t_multidriven_class1.v delete mode 100755 test_regress/t/t_multidriven_class2.py delete mode 100644 test_regress/t/t_multidriven_class2.v delete mode 100755 test_regress/t/t_multidriven_class3.py delete mode 100644 test_regress/t/t_multidriven_class3.v delete mode 100755 test_regress/t/t_multidriven_class4.py delete mode 100644 test_regress/t/t_multidriven_class4.v delete mode 100755 test_regress/t/t_multidriven_classf0.py delete mode 100644 test_regress/t/t_multidriven_classf0.v delete mode 100755 test_regress/t/t_multidriven_classf1.py delete mode 100644 test_regress/t/t_multidriven_classf1.v diff --git a/test_regress/t/t_multidriven_class0.py b/test_regress/t/t_multidriven_class.py old mode 100755 new mode 100644 similarity index 100% rename from test_regress/t/t_multidriven_class0.py rename to test_regress/t/t_multidriven_class.py diff --git a/test_regress/t/t_multidriven_class.v b/test_regress/t/t_multidriven_class.v new file mode 100644 index 000000000..9e93c55b6 --- /dev/null +++ b/test_regress/t/t_multidriven_class.v @@ -0,0 +1,284 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty. +// SPDX-License-Identifier: CC0-1.0 + +// Consolidated class-based task/function multidriven tests +// (formerly t_multidriven_class{0,1,2,3,4,f0,f1}.v) + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +//---------------------------------------------------------------------- +// class0: class task writes through ref argument (direct assignment + class task in same always_comb) + +class C0; + task automatic set1(ref logic q); + q = 1'b1; + endtask + task automatic set0(ref logic q); + q = 1'b0; + endtask +endclass + +module class0 #()( + input logic sel + ,output logic val +); + + logic l0; + C0 c; + + initial c = new; + + always_comb begin + l0 = 1'b0; + if (sel) begin + c.set1(l0); + end + end + + assign val = l0; + +endmodule + +//---------------------------------------------------------------------- +// class1: class task chain - nested method calls write through ref in same always_comb + +class C1; + task automatic inner(inout logic q); + q = 1'b1; + endtask + task automatic outer(inout logic q); + inner(q); + endtask +endclass + +module class1 #()( + input logic sel + ,output logic val +); + + logic l0; + C1 c; + + initial c = new; + + always_comb begin + l0 = 1'b0; + if (sel) begin + c.outer(l0); + end + end + + assign val = l0; + +endmodule + +//---------------------------------------------------------------------- +// class2: class handle passed through module port - class method writes through ref + +class C2; + task automatic set1(ref logic q); + q = 1'b1; + endtask +endclass + +module class2 #()( + input logic sel + ,output logic val + ,C2 c +); + + logic l0; + + always_comb begin + l0 = 1'b0; + if (sel) begin + c.set1(l0); + end + end + + assign val = l0; + +endmodule + +//---------------------------------------------------------------------- +// class3: static class task - call via class scope, writes through ref in same always_comb + +class C3; + static task automatic set1(ref logic q); + q = 1'b1; + endtask +endclass + +module class3 #()( + input logic sel + ,output logic val +); + + logic l0; + + always_comb begin + l0 = 1'b0; + if (sel) begin + C3::set1(l0); + end + end + + assign val = l0; + +endmodule + +//---------------------------------------------------------------------- +// class4: class composition - one class calls another task, ultimately writes through ref + +class C4Inner; + task automatic set1(ref logic q); + q = 1'b1; + endtask +endclass + +class C4Outer; + C4Inner inner; + function new(); + inner = new; + endfunction + task automatic set1(ref logic q); + inner.set1(q); + endtask +endclass + +module class4 #()( + input logic sel + ,output logic val +); + + logic l0; + C4Outer c; + + initial c = new; + + always_comb begin + l0 = 1'b0; + if (sel) begin + c.set1(l0); + end + end + + assign val = l0; + +endmodule + +//---------------------------------------------------------------------- +// classf0: class function returns value - always_comb writes var directly + via class function call + +class Cf0; + function automatic logic ret1(); + return 1'b1; + endfunction +endclass + +module classf0 #()( + input logic sel + ,output logic val +); + + logic l0; + Cf0 c; + + initial c = new; + + always_comb begin + l0 = 1'b0; + if (sel) begin + l0 = c.ret1(); + end + end + + assign val = l0; + +endmodule + +//---------------------------------------------------------------------- +// classf1: static class function returns value - always_comb uses class scope call + +class Cf1; + static function automatic logic ret1(); + return 1'b1; + endfunction +endclass + +module classf1 #()( + input logic sel + ,output logic val +); + + logic l0; + + always_comb begin + l0 = 1'b0; + if (sel) begin + l0 = Cf1::ret1(); + end + end + + assign val = l0; + +endmodule + +//---------------------------------------------------------------------- +// Shared TB + +module m_tb#()(); + + logic sel; + + logic val0, val1, val2, val3, val4, valf0, valf1; + + C2 c2; + initial c2 = new; + + class0 u0(.sel(sel), .val(val0)); + class1 u1(.sel(sel), .val(val1)); + class2 u2(.sel(sel), .val(val2), .c(c2)); + class3 u3(.sel(sel), .val(val3)); + class4 u4(.sel(sel), .val(val4)); + classf0 uf0(.sel(sel), .val(valf0)); + classf1 uf1(.sel(sel), .val(valf1)); + + task automatic check_all(input logic exp); + `checkd(val0, exp); + `checkd(val1, exp); + `checkd(val2, exp); + `checkd(val3, exp); + `checkd(val4, exp); + `checkd(valf0, exp); + `checkd(valf1, exp); + endtask + + initial begin + #1; + sel = 'b0; + #1; + check_all(1'b0); + + sel = 'b1; + #1; + check_all(1'b1); + + sel = 'b0; + #1; + check_all(1'b0); + end + + initial begin + #5; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test_regress/t/t_multidriven_class0.v b/test_regress/t/t_multidriven_class0.v deleted file mode 100644 index 6df099a7e..000000000 --- a/test_regress/t/t_multidriven_class0.v +++ /dev/null @@ -1,72 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed into the Public Domain, for any use, -// without warranty. -// SPDX-License-Identifier: CC0-1.0 - -// class task writes through ref argument (direct assignment + class task in same always_comb) - -// verilog_format: off -`define stop $stop -`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); -// verilog_format: on - -class C; - task automatic set1(ref logic q); - q = 1'b1; - endtask - task automatic set0(ref logic q); - q = 1'b0; - endtask -endclass - -module mod #()( - input logic sel - ,output logic val -); - - logic l0; - C c; - - initial c = new; - - always_comb begin - l0 = 1'b0; - if (sel) begin - c.set1(l0); - end - end - - assign val = l0; - -endmodule - -module m_tb#()(); - - logic sel, val; - - mod m( - .sel(sel) - ,.val(val) - ); - - initial begin - #1; - sel = 'b0; - #1; - `checkd(val, 1'b0); - sel = 'b1; - #1; - `checkd(val, 1'b1); - sel = 'b0; - #1; - `checkd(val, 1'b0); - end - - initial begin - #5; - $write("*-* All Finished *-*\n"); - $finish; - end - -endmodule diff --git a/test_regress/t/t_multidriven_class1.py b/test_regress/t/t_multidriven_class1.py deleted file mode 100755 index c6e56559a..000000000 --- a/test_regress/t/t_multidriven_class1.py +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') - -test.compile(verilator_flags2=["--binary"]) - -test.execute() - -test.passes() diff --git a/test_regress/t/t_multidriven_class1.v b/test_regress/t/t_multidriven_class1.v deleted file mode 100644 index 773f051e9..000000000 --- a/test_regress/t/t_multidriven_class1.v +++ /dev/null @@ -1,72 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed into the Public Domain, for any use, -// without warranty. -// SPDX-License-Identifier: CC0-1.0 - -// class task chain - nested method calls write through ref in same always_comb - -// verilog_format: off -`define stop $stop -`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); -// verilog_format: on - -class C; - task automatic inner(inout logic q); - q = 1'b1; - endtask - task automatic outer(inout logic q); - inner(q); - endtask -endclass - -module mod #()( - input logic sel - ,output logic val -); - - logic l0; - C c; - - initial c = new; - - always_comb begin - l0 = 1'b0; - if (sel) begin - c.outer(l0); - end - end - - assign val = l0; - -endmodule - -module m_tb#()(); - - logic sel, val; - - mod m( - .sel(sel) - ,.val(val) - ); - - initial begin - #1; - sel = 'b0; - #1; - `checkd(val, 1'b0); - sel = 'b1; - #1; - `checkd(val, 1'b1); - sel = 'b0; - #1; - `checkd(val, 1'b0); - end - - initial begin - #5; - $write("*-* All Finished *-*\n"); - $finish; - end - -endmodule diff --git a/test_regress/t/t_multidriven_class2.py b/test_regress/t/t_multidriven_class2.py deleted file mode 100755 index c6e56559a..000000000 --- a/test_regress/t/t_multidriven_class2.py +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') - -test.compile(verilator_flags2=["--binary"]) - -test.execute() - -test.passes() diff --git a/test_regress/t/t_multidriven_class2.v b/test_regress/t/t_multidriven_class2.v deleted file mode 100644 index dff4ec2cc..000000000 --- a/test_regress/t/t_multidriven_class2.v +++ /dev/null @@ -1,71 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed into the Public Domain, for any use, -// without warranty. -// SPDX-License-Identifier: CC0-1.0 - -// class handle passed through module port - class method writes through ref - -// verilog_format: off -`define stop $stop -`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); -// verilog_format: on - -class C; - task automatic set1(ref logic q); - q = 1'b1; - endtask -endclass - -module mod #()( - input logic sel - ,output logic val - ,C c -); - - logic l0; - - always_comb begin - l0 = 1'b0; - if (sel) begin - c.set1(l0); - end - end - - assign val = l0; - -endmodule - -module m_tb#()(); - - logic sel, val; - C c; - - initial c = new; - - mod m( - .sel(sel) - ,.val(val) - ,.c(c) - ); - - initial begin - #1; - sel = 'b0; - #1; - `checkd(val, 1'b0); - sel = 'b1; - #1; - `checkd(val, 1'b1); - sel = 'b0; - #1; - `checkd(val, 1'b0); - end - - initial begin - #5; - $write("*-* All Finished *-*\n"); - $finish; - end - -endmodule diff --git a/test_regress/t/t_multidriven_class3.py b/test_regress/t/t_multidriven_class3.py deleted file mode 100755 index c6e56559a..000000000 --- a/test_regress/t/t_multidriven_class3.py +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') - -test.compile(verilator_flags2=["--binary"]) - -test.execute() - -test.passes() diff --git a/test_regress/t/t_multidriven_class3.v b/test_regress/t/t_multidriven_class3.v deleted file mode 100644 index 1c0c4eedd..000000000 --- a/test_regress/t/t_multidriven_class3.v +++ /dev/null @@ -1,66 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed into the Public Domain, for any use, -// without warranty. -// SPDX-License-Identifier: CC0-1.0 - -// static class task - call via class scope, writes through ref in same always_comb - -// verilog_format: off -`define stop $stop -`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); -// verilog_format: on - -class C; - static task automatic set1(ref logic q); - q = 1'b1; - endtask -endclass - -module mod #()( - input logic sel - ,output logic val -); - - logic l0; - - always_comb begin - l0 = 1'b0; - if (sel) begin - C::set1(l0); - end - end - - assign val = l0; - -endmodule - -module m_tb#()(); - - logic sel, val; - - mod m( - .sel(sel) - ,.val(val) - ); - - initial begin - #1; - sel = 'b0; - #1; - `checkd(val, 1'b0); - sel = 'b1; - #1; - `checkd(val, 1'b1); - sel = 'b0; - #1; - `checkd(val, 1'b0); - end - - initial begin - #5; - $write("*-* All Finished *-*\n"); - $finish; - end - -endmodule diff --git a/test_regress/t/t_multidriven_class4.py b/test_regress/t/t_multidriven_class4.py deleted file mode 100755 index c6e56559a..000000000 --- a/test_regress/t/t_multidriven_class4.py +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') - -test.compile(verilator_flags2=["--binary"]) - -test.execute() - -test.passes() diff --git a/test_regress/t/t_multidriven_class4.v b/test_regress/t/t_multidriven_class4.v deleted file mode 100644 index 41c91c415..000000000 --- a/test_regress/t/t_multidriven_class4.v +++ /dev/null @@ -1,79 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed into the Public Domain, for any use, -// without warranty. -// SPDX-License-Identifier: CC0-1.0 - -// class composition - one class calls another task, ultimately writes through ref - -// verilog_format: off -`define stop $stop -`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); -// verilog_format: on - -class CInner; - task automatic set1(ref logic q); - q = 1'b1; - endtask -endclass - -class COuter; - CInner inner; - function new(); - inner = new; - endfunction - task automatic set1(ref logic q); - inner.set1(q); - endtask -endclass - -module mod #()( - input logic sel - ,output logic val -); - - logic l0; - COuter c; - - initial c = new; - - always_comb begin - l0 = 1'b0; - if (sel) begin - c.set1(l0); - end - end - - assign val = l0; - -endmodule - -module m_tb#()(); - - logic sel, val; - - mod m( - .sel(sel) - ,.val(val) - ); - - initial begin - #1; - sel = 'b0; - #1; - `checkd(val, 1'b0); - sel = 'b1; - #1; - `checkd(val, 1'b1); - sel = 'b0; - #1; - `checkd(val, 1'b0); - end - - initial begin - #5; - $write("*-* All Finished *-*\n"); - $finish; - end - -endmodule diff --git a/test_regress/t/t_multidriven_classf0.py b/test_regress/t/t_multidriven_classf0.py deleted file mode 100755 index c6e56559a..000000000 --- a/test_regress/t/t_multidriven_classf0.py +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') - -test.compile(verilator_flags2=["--binary"]) - -test.execute() - -test.passes() diff --git a/test_regress/t/t_multidriven_classf0.v b/test_regress/t/t_multidriven_classf0.v deleted file mode 100644 index c5c996887..000000000 --- a/test_regress/t/t_multidriven_classf0.v +++ /dev/null @@ -1,69 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed into the Public Domain, for any use, -// without warranty. -// SPDX-License-Identifier: CC0-1.0 - -// class function returns value - always_comb writes var directly + via class function call - -// verilog_format: off -`define stop $stop -`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); -// verilog_format: on - -class C; - function automatic logic ret1(); - return 1'b1; - endfunction -endclass - -module mod #()( - input logic sel - ,output logic val -); - - logic l0; - C c; - - initial c = new; - - always_comb begin - l0 = 1'b0; - if (sel) begin - l0 = c.ret1(); - end - end - - assign val = l0; - -endmodule - -module m_tb#()(); - - logic sel, val; - - mod m( - .sel(sel) - ,.val(val) - ); - - initial begin - #1; - sel = 'b0; - #1; - `checkd(val, 1'b0); - sel = 'b1; - #1; - `checkd(val, 1'b1); - sel = 'b0; - #1; - `checkd(val, 1'b0); - end - - initial begin - #5; - $write("*-* All Finished *-*\n"); - $finish; - end - -endmodule diff --git a/test_regress/t/t_multidriven_classf1.py b/test_regress/t/t_multidriven_classf1.py deleted file mode 100755 index c6e56559a..000000000 --- a/test_regress/t/t_multidriven_classf1.py +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') - -test.compile(verilator_flags2=["--binary"]) - -test.execute() - -test.passes() diff --git a/test_regress/t/t_multidriven_classf1.v b/test_regress/t/t_multidriven_classf1.v deleted file mode 100644 index 9b8efd46f..000000000 --- a/test_regress/t/t_multidriven_classf1.v +++ /dev/null @@ -1,66 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed into the Public Domain, for any use, -// without warranty. -// SPDX-License-Identifier: CC0-1.0 - -// static class function returns value - always_comb uses class scope call - -// verilog_format: off -`define stop $stop -`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); -// verilog_format: on - -class C; - static function automatic logic ret1(); - return 1'b1; - endfunction -endclass - -module mod #()( - input logic sel - ,output logic val -); - - logic l0; - - always_comb begin - l0 = 1'b0; - if (sel) begin - l0 = C::ret1(); - end - end - - assign val = l0; - -endmodule - -module m_tb#()(); - - logic sel, val; - - mod m( - .sel(sel) - ,.val(val) - ); - - initial begin - #1; - sel = 'b0; - #1; - `checkd(val, 1'b0); - sel = 'b1; - #1; - `checkd(val, 1'b1); - sel = 'b0; - #1; - `checkd(val, 1'b0); - end - - initial begin - #5; - $write("*-* All Finished *-*\n"); - $finish; - end - -endmodule