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Fix sign extension of signed compared with unsigned case items (#5968).

This commit is contained in:
Wilson Snyder 2025-04-28 22:22:50 -04:00
parent 3658e5f0f1
commit 8da539ed8a
3 changed files with 37 additions and 5 deletions
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2
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@ -13,6 +13,8 @@ Verilator 5.037 devel
**Other:** **Other:**
* Fix sign extension of signed compared with unsigned case items (#5968).
Verilator 5.036 2025-04-27 Verilator 5.036 2025-04-27
========================== ==========================

2
src/V3Width.cpp
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@ -5076,7 +5076,7 @@ class WidthVisitor final : public VNVisitor {
} }
// Apply width // Apply width
iterateCheck(nodep, "Case expression", nodep->exprp(), CONTEXT_DET, FINAL, subDTypep, iterateCheck(nodep, "Case expression", nodep->exprp(), CONTEXT_DET, FINAL, subDTypep,
EXTEND_LHS); EXTEND_EXP);
for (AstCaseItem* itemp = nodep->itemsp(); itemp; for (AstCaseItem* itemp = nodep->itemsp(); itemp;
itemp = VN_AS(itemp->nextp(), CaseItem)) { itemp = VN_AS(itemp->nextp(), CaseItem)) {
for (AstNode *nextcp, *condp = itemp->condsp(); condp; condp = nextcp) { for (AstNode *nextcp, *condp = itemp->condsp(); condp; condp = nextcp) {

38
test_regress/t/t_math_signed3.v
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@ -48,7 +48,13 @@ module t (/*AUTOARG*/);
wire [5:0] cond_b = 1'b0 ? 3'sb111 : 5'sb11111; wire [5:0] cond_b = 1'b0 ? 3'sb111 : 5'sb11111;
initial `checkh(cond_b, 6'b111111); initial `checkh(cond_b, 6'b111111);
bit cmp;
initial begin initial begin
`ifndef VERILATOR
#1;
`endif
// verilator lint_on WIDTH // verilator lint_on WIDTH
`checkh(bug729_yuu, 1'b0); `checkh(bug729_yuu, 1'b0);
`checkh(bug729_ysu, 1'b0); `checkh(bug729_ysu, 1'b0);
@ -81,13 +87,37 @@ module t (/*AUTOARG*/);
bug349_s = 4'sb1111 - 5'b00001; bug349_s = 4'sb1111 - 5'b00001;
`checkh(bug349_s,33'he); `checkh(bug349_s,33'he);
cmp = 3'sb111 == 4'b111;
`checkh(cmp, 1);
cmp = 3'sb111 == 4'sb111;
`checkh(cmp, 0);
cmp = 3'sb111 != 4'b111;
`checkh(cmp, 0);
cmp = 3'sb111 != 4'sb111;
`checkh(cmp, 1);
cmp = 3'sb111 === 4'b111;
`checkh(cmp, 1);
cmp = 3'sb111 === 4'sb111;
`checkh(cmp, 0);
case (2'sb11) case (2'sb11)
4'b1111: ; 4'b1111: $stop;
default: ;
endcase
case (sb11)
4'b1111: $stop;
default: ;
endcase
case (2'sb11)
4'sb1111: ;
default: $stop; default: $stop;
endcase endcase
case (sb11) case (sb11)
4'b1111: ; 4'sb1111: ;
default: $stop; default: $stop;
endcase endcase
@ -96,7 +126,7 @@ module t (/*AUTOARG*/);
end end
endmodule endmodule
module sub (input [3:0] a, module sub(input [3:0] a,
output [3:0] z); output [3:0] z);
assign z = a; assign z = a;
endmodule endmodule