From 8da539ed8a261a34b744018d8eda6055f91a3e68 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Mon, 28 Apr 2025 22:22:50 -0400
Subject: [PATCH] Fix sign extension of signed compared with unsigned case
 items (#5968).

---
 Changes                         |  2 ++
 src/V3Width.cpp                 |  2 +-
 test_regress/t/t_math_signed3.v | 38 +++++++++++++++++++++++++++++----
 3 files changed, 37 insertions(+), 5 deletions(-)

diff --git a/Changes b/Changes
index 69deeb0ef..22cb7979c 100644
--- a/Changes
+++ b/Changes
@@ -13,6 +13,8 @@ Verilator 5.037 devel
 
 **Other:**
 
+* Fix sign extension of signed compared with unsigned case items (#5968).
+
 
 Verilator 5.036 2025-04-27
 ==========================
diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index cea0cb007..1f5f5ae18 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -5076,7 +5076,7 @@ class WidthVisitor final : public VNVisitor {
         }
         // Apply width
         iterateCheck(nodep, "Case expression", nodep->exprp(), CONTEXT_DET, FINAL, subDTypep,
-                     EXTEND_LHS);
+                     EXTEND_EXP);
         for (AstCaseItem* itemp = nodep->itemsp(); itemp;
              itemp = VN_AS(itemp->nextp(), CaseItem)) {
             for (AstNode *nextcp, *condp = itemp->condsp(); condp; condp = nextcp) {
diff --git a/test_regress/t/t_math_signed3.v b/test_regress/t/t_math_signed3.v
index 03b20e753..24970ac5e 100644
--- a/test_regress/t/t_math_signed3.v
+++ b/test_regress/t/t_math_signed3.v
@@ -48,7 +48,13 @@ module t (/*AUTOARG*/);
    wire [5:0]        cond_b = 1'b0 ? 3'sb111 : 5'sb11111;
    initial `checkh(cond_b, 6'b111111);
 
+   bit cmp;
+
    initial begin
+`ifndef VERILATOR
+      #1;
+`endif
+
       // verilator lint_on WIDTH
       `checkh(bug729_yuu, 1'b0);
       `checkh(bug729_ysu, 1'b0);
@@ -81,13 +87,37 @@ module t (/*AUTOARG*/);
       bug349_s = 4'sb1111 - 5'b00001;
       `checkh(bug349_s,33'he);
 
+      cmp = 3'sb111 == 4'b111;
+      `checkh(cmp, 1);
+      cmp = 3'sb111 == 4'sb111;
+      `checkh(cmp, 0);
+      cmp = 3'sb111 != 4'b111;
+      `checkh(cmp, 0);
+      cmp = 3'sb111 != 4'sb111;
+      `checkh(cmp, 1);
+
+      cmp = 3'sb111 === 4'b111;
+      `checkh(cmp, 1);
+      cmp = 3'sb111 === 4'sb111;
+      `checkh(cmp, 0);
+
       case (2'sb11)
-        4'b1111: ;
+        4'b1111: $stop;
+        default: ;
+      endcase
+
+      case (sb11)
+        4'b1111: $stop;
+        default: ;
+      endcase
+
+      case (2'sb11)
+        4'sb1111: ;
         default: $stop;
       endcase
 
       case (sb11)
-        4'b1111: ;
+        4'sb1111: ;
         default: $stop;
       endcase
 
@@ -96,7 +126,7 @@ module t (/*AUTOARG*/);
    end
 endmodule
 
-module sub (input [3:0] a,
-            output [3:0] z);
+module sub(input [3:0] a,
+           output [3:0] z);
    assign z = a;
 endmodule