Tests: Add elaboration info test.
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@ -6,6 +6,7 @@
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module t (/*AUTOARG*/);
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module t (/*AUTOARG*/);
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if (0) begin
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if (0) begin
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$info("User compile-time info");
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$warning("User compile-time warning");
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$warning("User compile-time warning");
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$error("User compile-time error");
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$error("User compile-time error");
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end
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end
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@ -0,0 +1,5 @@
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[0] -Info: t_assert_comp_bad.v:9: Assertion failed in top.t.genblk1: User compile-time info
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[0] %Warning: t_assert_comp_bad.v:10: Assertion failed in top.t.genblk1: User compile-time warning
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[0] %Error: t_assert_comp_bad.v:11: Assertion failed in top.t.genblk1: User compile-time error
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%Error: t/t_assert_comp_bad.v:11: Verilog $stop
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Aborting...
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@ -12,15 +12,13 @@ scenarios(simulator => 1);
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compile(
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compile(
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verilator_flags2 => ['--assert'],
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verilator_flags2 => ['--assert'],
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nc_flags2 => ['+assert'],
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nc_flags2 => ['+assert'],
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vcs_flags2 => ['-assert svaext'],
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);
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);
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execute(
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execute(
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check_finished => 0,
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check_finished => 0,
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fails => 1,
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fails => 1,
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expect =>
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expect_filename => $Self->{golden_filename},
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'.*%Warning: t_assert_comp_bad.v:\d+: Assertion failed in top.t.genblk1: User compile-time warning
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.*%Error: t_assert_comp_bad.v:\d+: Assertion failed in top.t.genblk1: User compile-time error'
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);
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);
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ok(1);
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ok(1);
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@ -6,6 +6,7 @@
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module t (/*AUTOARG*/);
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module t (/*AUTOARG*/);
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if (1) begin
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if (1) begin
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$info("User compile-time info");
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$warning("User compile-time warning");
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$warning("User compile-time warning");
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$error("User compile-time error");
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$error("User compile-time error");
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end
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end
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