Fix broken support of unassigned virtual interfaces (#6253) (#6338)

* Fix broken support of unassigned virtual interfaces

Unassigned virtual interface support added by #6245 is broken - PR marks
dead module as alive - we can't do that as once a module is dead it
needs to remain dead because earlier steps (e.g. port resolution) have
already been skipped.

This commit handles unassigned virtual interfaces at the beginning of
first pass of LinkDot (so it is never marked as dead, and no linking
steps are getting skipped).

Fixes #6253.

* Apply suggestions from code review

Co-authored-by: Wilson Snyder <[email protected]>

* Apply 'make format'

* Revert add of redundant iterateChildren() call

* Add original test case

---------

Co-authored-by: Wilson Snyder <[email protected]>
Co-authored-by: github action <[email protected]>

test_regress/t/t_interface_virtual_missing_bad.v

@@ -0,0 +1,15 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Antmicro.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/);
+
+   virtual foo vif;
+
+   initial begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule