Fix incorrect Non-ANSI I/O declaration conflict error (#6258) broke with #bd1ac038

test_regress/t/t_func_nansi_bad.out

@@ -1,44 +0,0 @@
-%Error: t/t_func_nansi_bad.v:13:14: Non-ANSI I/O declaration of signal conflicts with type declaration: 'bad1'
-   13 |     shortint bad1;   
-      |              ^~~~
-        t/t_func_nansi_bad.v:12:18: ... Location of other declaration
-   12 |     input [15:0] bad1;
-      |                  ^~~~
-        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
-%Error: t/t_func_nansi_bad.v:18:7: Non-ANSI I/O declaration of signal conflicts with type declaration: 'bad2'
-   18 |     T bad2;   
-      |       ^~~~
-        t/t_func_nansi_bad.v:17:18: ... Location of other declaration
-   17 |     input [31:0] bad2;
-      |                  ^~~~
-%Error: t/t_func_nansi_bad.v:23:15: Non-ANSI I/O declaration of signal conflicts with type declaration: 'bad3'
-   23 |     reg [3:0] bad3;   
-      |               ^~~~
-        t/t_func_nansi_bad.v:22:17: ... Location of other declaration
-   22 |     input [7:0] bad3;
-      |                 ^~~~
-%Error: t/t_func_nansi_bad.v:28:9: Non-ANSI I/O declaration of signal conflicts with type declaration: 'bad4'
-   28 |     reg bad4;
-      |         ^~~~
-        t/t_func_nansi_bad.v:27:17: ... Location of other declaration
-   27 |     input [7:0] bad4;
-      |                 ^~~~
-%Error: t/t_func_nansi_bad.v:29:9: Duplicate declaration of signal: 'bad4'
-   29 |     reg bad4;   
-      |         ^~~~
-        t/t_func_nansi_bad.v:27:17: ... Location of original declaration
-   27 |     input [7:0] bad4;
-      |                 ^~~~
-%Error: t/t_func_nansi_bad.v:34:17: Duplicate declaration of signal: 'bad5'
-   34 |     input [7:0] bad5;   
-      |                 ^~~~
-        t/t_func_nansi_bad.v:33:17: ... Location of original declaration
-   33 |     input [7:0] bad5;
-      |                 ^~~~
-%Error: t/t_func_nansi_bad.v:35:9: Non-ANSI I/O declaration of signal conflicts with type declaration: 'bad5'
-   35 |     reg bad5;
-      |         ^~~~
-        t/t_func_nansi_bad.v:33:17: ... Location of other declaration
-   33 |     input [7:0] bad5;
-      |                 ^~~~
-%Error: Exiting due to

test_regress/t/t_func_nansi_dup_bad.out

@@ -0,0 +1,14 @@
+%Error: t/t_func_nansi_dup_bad.v:14:9: Duplicate declaration of signal: 'bad4'
+   14 |     reg bad4;   
+      |         ^~~~
+        t/t_func_nansi_dup_bad.v:12:17: ... Location of original declaration
+   12 |     input [7:0] bad4;
+      |                 ^~~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
+%Error: t/t_func_nansi_dup_bad.v:19:17: Duplicate declaration of signal: 'bad5'
+   19 |     input [7:0] bad5;   
+      |                 ^~~~
+        t/t_func_nansi_dup_bad.v:18:17: ... Location of original declaration
+   18 |     input [7:0] bad5;
+      |                 ^~~~
+%Error: Exiting due to

test_regress/t/t_func_nansi_dup_bad.v

@@ -0,0 +1,23 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+typedef int T;
+
+module test;
+
+  task t4;
+    input [7:0] bad4;
+    reg bad4;
+    reg bad4;  // <--- Error (duplicate)
+  endtask
+
+  task t5;
+    input [7:0] bad5;
+    input [7:0] bad5;  // <--- Error (duplicate)
+    reg bad5;
+  endtask
+
+endmodule

test_regress/t/t_func_nansi_mism_bad.out

@@ -0,0 +1,20 @@
+%Error: t/t_func_nansi_mism_bad.v:12:11: Non-ANSI I/O declaration of signal conflicts with type declaration: 'bad1'
+   12 |     input [15:0] bad1;
+      |           ^
+        t/t_func_nansi_mism_bad.v:13:5: ... Location of other declaration
+   13 |     shortint bad1;   
+      |     ^~~~~~~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
+%Error: t/t_func_nansi_mism_bad.v:17:11: Non-ANSI I/O declaration of signal conflicts with type declaration: 'bad2'
+   17 |     input [31:0] bad2;
+      |           ^
+        t/t_func_nansi_mism_bad.v:18:5: ... Location of other declaration
+   18 |     T bad2;   
+      |     ^
+%Error: t/t_func_nansi_mism_bad.v:22:11: Non-ANSI I/O declaration of signal conflicts with type declaration: 'bad3'
+   22 |     input [7:0] bad3;
+      |           ^
+        t/t_func_nansi_mism_bad.v:23:5: ... Location of other declaration
+   23 |     reg [3:0] bad3;   
+      |     ^~~
+%Error: Exiting due to

test_regress/t/t_func_nansi_mism_bad.v

@@ -23,16 +23,4 @@ module test;
     reg [3:0] bad3;  // <--- Error (type doesn't match above)
   endtask
 
-  task t4;
-    input [7:0] bad4;
-    reg bad4;
-    reg bad4;  // <--- Error (duplicate)
-  endtask
-
-  task t5;
-    input [7:0] bad5;
-    input [7:0] bad5;  // <--- Error (duplicate)
-    reg bad5;
-  endtask
-
 endmodule

test_regress/t/t_inst_nansi_bad.out

@@ -1,32 +0,0 @@
-%Error: t/t_inst_nansi_bad.v:14:12: Non-ANSI I/O declaration of signal conflicts with type declaration: 'bad1'
-   14 |   shortint bad1;   
-      |            ^~~~
-        t/t_inst_nansi_bad.v:13:17: ... Location of other declaration
-   13 |   output [15:0] bad1;
-      |                 ^~~~
-        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
-%Error: t/t_inst_nansi_bad.v:17:5: Non-ANSI I/O declaration of signal conflicts with type declaration: 'bad2'
-   17 |   T bad2;   
-      |     ^~~~
-        t/t_inst_nansi_bad.v:16:17: ... Location of other declaration
-   16 |   output [31:0] bad2;
-      |                 ^~~~
-%Error: t/t_inst_nansi_bad.v:20:13: Non-ANSI I/O declaration of signal conflicts with type declaration: 'bad3'
-   20 |   reg [7:0] bad3;   
-      |             ^~~~
-        t/t_inst_nansi_bad.v:19:16: ... Location of other declaration
-   19 |   output [3:0] bad3;
-      |                ^~~~
-%Error: t/t_inst_nansi_bad.v:24:7: Duplicate declaration of signal: 'bad4'
-   24 |   reg bad4;   
-      |       ^~~~
-        t/t_inst_nansi_bad.v:22:10: ... Location of original declaration
-   22 |   output bad4;
-      |          ^~~~
-%Error: t/t_inst_nansi_bad.v:27:10: Duplicate declaration of signal: 'bad5'
-   27 |   output bad5;   
-      |          ^~~~
-        t/t_inst_nansi_bad.v:26:10: ... Location of original declaration
-   26 |   output bad5;
-      |          ^~~~
-%Error: Exiting due to

test_regress/t/t_inst_nansi_dup_bad.out

@@ -0,0 +1,14 @@
+%Error: t/t_inst_nansi_dup_bad.v:16:7: Duplicate declaration of signal: 'bad4'
+   16 |   reg bad4;   
+      |       ^~~~
+        t/t_inst_nansi_dup_bad.v:14:10: ... Location of original declaration
+   14 |   output bad4;
+      |          ^~~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
+%Error: t/t_inst_nansi_dup_bad.v:19:10: Duplicate declaration of signal: 'bad5'
+   19 |   output bad5;   
+      |          ^~~~
+        t/t_inst_nansi_dup_bad.v:18:10: ... Location of original declaration
+   18 |   output bad5;
+      |          ^~~~
+%Error: Exiting due to

test_regress/t/t_inst_nansi_dup_bad.py

@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('linter')
+
+test.lint(fails=True, expect_filename=test.golden_filename)
+
+test.passes()

test_regress/t/t_inst_nansi_dup_bad.v

@@ -0,0 +1,22 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+typedef int T;
+
+module test (  /*AUTOARG*/
+  // Outputs
+  bad4, bad5
+  );
+
+  output bad4;
+  reg bad4;
+  reg bad4;  // <--- Error (duplicate)
+
+  output bad5;
+  output bad5;  // <--- Error (duplicate)
+  reg bad5;  // <--- Error (duplicate)
+
+endmodule

test_regress/t/t_inst_nansi_mism_bad.out

@@ -0,0 +1,26 @@
+%Error: t/t_inst_nansi_mism_bad.v:13:10: Non-ANSI I/O declaration of signal conflicts with type declaration: 'bad1'
+   13 |   output [15:0] bad1;
+      |          ^
+        t/t_inst_nansi_mism_bad.v:14:3: ... Location of other declaration
+   14 |   shortint bad1;   
+      |   ^~~~~~~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
+%Error: t/t_inst_nansi_mism_bad.v:16:10: Non-ANSI I/O declaration of signal conflicts with type declaration: 'bad2'
+   16 |   output [31:0] bad2;
+      |          ^
+        t/t_inst_nansi_mism_bad.v:17:3: ... Location of other declaration
+   17 |   T bad2;   
+      |   ^
+%Error: t/t_inst_nansi_mism_bad.v:19:10: Non-ANSI I/O declaration of signal conflicts with type declaration: 'bad3'
+   19 |   output [3:0] bad3;
+      |          ^
+        t/t_inst_nansi_mism_bad.v:20:3: ... Location of other declaration
+   20 |   reg [7:0] bad3;   
+      |   ^~~
+%Error: t/t_inst_nansi_mism_bad.v:22:3: Non-ANSI I/O declaration of signal conflicts with type declaration: 'bad4'
+   22 |   reg [7:0] bad4;   
+      |   ^~~
+        t/t_inst_nansi_mism_bad.v:23:10: ... Location of other declaration
+   23 |   output [3:0] bad4;
+      |          ^
+%Error: Exiting due to

test_regress/t/t_inst_nansi_mism_bad.py

@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('linter')
+
+test.lint(fails=True, expect_filename=test.golden_filename)
+
+test.passes()

test_regress/t/t_inst_nansi_mism_bad.v

@@ -8,7 +8,7 @@ typedef int T;
 
 module test (  /*AUTOARG*/
   // Outputs
-  bad1, bad2, bad3, bad4, bad5
+  bad1, bad2, bad3, bad4
   );
   output [15:0] bad1;
   shortint bad1;  // <--- Error (type doesn't match above)
@@ -17,14 +17,9 @@ module test (  /*AUTOARG*/
   T bad2;  // <--- Error (type doesn't match above due to range)
 
   output [3:0] bad3;
-  reg [7:0] bad3;  // <--- Error (range doesn't match)
+  reg [7:0] bad3;  // <--- Error (range doesn't match) (output-before-reg)
 
-  output bad4;
-  reg bad4;
-  reg bad4;  // <--- Error (duplicate)
-
-  output bad5;
-  output bad5;  // <--- Error (duplicate)
-  reg bad5;  // <--- Error (duplicate)
+  reg [7:0] bad4;  // <--- Error (range doesn't match) (reg-before-output)
+  output [3:0] bad4;
 
 endmodule

test_regress/t/t_inst_nansi_param.py

@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('linter')
+
+test.compile()
+
+test.passes()

test_regress/t/t_inst_nansi_param.v

@@ -0,0 +1,16 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module sub(i);
+  parameter N = 3;
+  input [N : 0] i;  // Note 3:0 conflicts until parameterize
+  wire [2:0] i;
+endmodule
+
+module t;
+  wire [2:0] i;
+  sub #(.N(2)) sub(.i);
+endmodule