18 lines
365 B
Systemverilog
18 lines
365 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t;
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logic [15:0] foo [8];
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initial begin
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if (foo[1] != foo[1]) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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