From 85454f6083d9e5be7ffbd5e36965dcb749b6532f Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Fri, 5 Sep 2025 17:31:17 -0400
Subject: [PATCH] Fix wire array with initial assignment (#6391).

---
 Changes                                   | 1 +
 src/verilog.y                             | 7 +++++++
 test_regress/t/t_array_pattern_unpacked.v | 4 ++++
 3 files changed, 12 insertions(+)

diff --git a/Changes b/Changes
index ee47f384a..99745c5ee 100644
--- a/Changes
+++ b/Changes
@@ -19,6 +19,7 @@ Verilator 5.041 devel
 * Fix randomize local after parameters applied (#6371). [Alex Solomatnikov]
 * Fix package imports not found after parameters applied (#6373). [Alex Solomatnikov]
 * Fix COVERAGEIGN-ignored `get_inst_coverage` and other covergroup methods (#6383). [Alex Solomatnikov]
+* Fix wire array with initial assignment (#6391). [Alex Solomatnikov]
 
 
 Verilator 5.040 2025-08-30
diff --git a/src/verilog.y b/src/verilog.y
index 67d12719c..cb877bde8 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -3267,6 +3267,13 @@ netSig<varp>:                   // IEEE: net_decl_assignment -  one element from
                           AstNode::addNext<AstNode, AstNode>($$, assignp); }
         |       netId variable_dimensionList sigAttrListE
                         { $$ = VARDONEA($<fl>1, *$1, $2, $3); }
+        |       netId variable_dimensionList sigAttrListE '=' expr
+                        { AstDelay* const delayp = GRAMMARP->getNetDelay();
+                          AstAssignW* const assignp = new AstAssignW{$4, new AstParseRef{$<fl>1, VParseRefExp::PX_TEXT, *$1}, $5, delayp};
+                          $$ = VARDONEA($<fl>1, *$1, $2, $3);
+                          if (delayp) GRAMMARP->setNetDelay(delayp->cloneTree(false));
+                          if (GRAMMARP->m_netStrengthp) assignp->strengthSpecp(GRAMMARP->m_netStrengthp->cloneTree(false));
+                          AstNode::addNext<AstNode, AstNode>($$, assignp); }
         ;
 
 netId<strp>:
diff --git a/test_regress/t/t_array_pattern_unpacked.v b/test_regress/t/t_array_pattern_unpacked.v
index 60e710d92..58cddec25 100644
--- a/test_regress/t/t_array_pattern_unpacked.v
+++ b/test_regress/t/t_array_pattern_unpacked.v
@@ -7,10 +7,14 @@
 module t (/*AUTOARG*/);
 
    logic [3:0] array_simp [1:0] [3:0];  // descending range array
+   wire  [2:0] array_wire [1:0] = '{3'd1, 3'd2};
 
    int         irep[1:2][1:6];
 
    initial begin
+      if (array_wire[0] !== 3'd2) $stop;
+      if (array_wire[1] !== 3'd1) $stop;
+
       array_simp[0] = '{ 4'd3, 4'd2, 4'd1, 4'd0};
       if ({array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]}
           !== 16'h3210) $stop;