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[#73220] add t_trace_packed_struct_saif test

This commit is contained in:
Mateusz Gancarz 2025-02-25 15:21:52 +01:00
parent 99b5c5f6d2
commit 84950e56c4
2 changed files with 59 additions and 0 deletions
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38
test_regress/t/t_trace_packed_struct_saif.out Normal file
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(SAIFILE
(SAIFVERSION "2.0")
(DIRECTION "backward")
(DESIGN "t")
(DIVIDER / )
(TIMESCALE 1ps)
(DURATION 40)
(INSTANCE top
(NET
(clk (T0 25) (T1 15) (TX 0) (TC 7))
)
(INSTANCE t
(NET
(clk (T0 25) (T1 15) (TX 0) (TC 7))
(cnt\[0\] (T0 20) (T1 20) (TX 0) (TC 3))
(cnt\[1\] (T0 20) (T1 20) (TX 0) (TC 1))
(v[0]\[28\] (T0 0) (T1 40) (TX 0) (TC 1))
(v[0]\[29\] (T0 0) (T1 40) (TX 0) (TC 1))
(v[0]\[32\] (T0 0) (T1 40) (TX 0) (TC 1))
(v[0]\[60\] (T0 0) (T1 40) (TX 0) (TC 1))
(v[0]\[61\] (T0 0) (T1 40) (TX 0) (TC 1))
(v[0]\[65\] (T0 0) (T1 40) (TX 0) (TC 1))
(v[0]\[92\] (T0 0) (T1 40) (TX 0) (TC 1))
(v[0]\[93\] (T0 0) (T1 40) (TX 0) (TC 1))
(v[1]\[29\] (T0 0) (T1 40) (TX 0) (TC 1))
(v[1]\[32\] (T0 0) (T1 40) (TX 0) (TC 1))
(v[1]\[61\] (T0 0) (T1 40) (TX 0) (TC 1))
(v[1]\[65\] (T0 0) (T1 40) (TX 0) (TC 1))
(v[1]\[93\] (T0 0) (T1 40) (TX 0) (TC 1))
(v[2]\[28\] (T0 0) (T1 40) (TX 0) (TC 1))
(v[2]\[32\] (T0 0) (T1 40) (TX 0) (TC 1))
(v[2]\[60\] (T0 0) (T1 40) (TX 0) (TC 1))
(v[2]\[65\] (T0 0) (T1 40) (TX 0) (TC 1))
(v[2]\[92\] (T0 0) (T1 40) (TX 0) (TC 1))
)
)
)
)

21
test_regress/t/t_trace_packed_struct_saif.py Executable file
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#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.top_filename = "t/t_trace_packed_struct.v"
test.compile(v_flags2=["--trace-saif"])
test.execute()
test.saif_identical(test.trace_filename, test.golden_filename)
test.passes()