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Fix Verilator core dump on wide integer divides, bug178.

This commit is contained in:
Wilson Snyder 2009-11-10 10:44:50 -05:00
parent 8487d67f00
commit 82d917c2c5
2 changed files with 4 additions and 2 deletions
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@ -18,6 +18,8 @@ indicates the contributor was also the author of the fix; Thanks!
*** Add VARHIDDEN warning when signal name hides module name.
**** Fix Verilator core dump on wide integer divides, bug178. [Bryon Bradley]
* Verilator 3.720 2009/10/26
** Support little endian bit vectors ("reg [0:2] x;").

4
src/V3Number.cpp
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@ -1177,8 +1177,8 @@ V3Number& V3Number::opModDivGuts(const V3Number& lhs, const V3Number& rhs, bool
uint32_t vn[VL_MULS_MAX_WORDS+1]; // v normalized
// Zero for ease of debugging and to save having to zero for shifts
for (int i=0; i<6; i++) { un[i]=vn[i]=m_value[i]=0; }
for (int i=6; i<words+1; i++) { un[i]=vn[i]=0; } // +1 as vn may get extra word
for (int i=0; i<words; i++) { m_value[i]=0; }
for (int i=0; i<words+1; i++) { un[i]=vn[i]=0; } // +1 as vn may get extra word
// Algorithm requires divisor MSB to be set
// Copy and shift to normalize divisor so MSB of vn[vw-1] is set