diff --git a/Changes b/Changes
index d185aee2b..24c67f992 100644
--- a/Changes
+++ b/Changes
@@ -18,6 +18,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 ***  Add VARHIDDEN warning when signal name hides module name.
 
+**** Fix Verilator core dump on wide integer divides, bug178. [Bryon Bradley]
+
 * Verilator 3.720 2009/10/26
 
 **   Support little endian bit vectors ("reg [0:2] x;").
diff --git a/src/V3Number.cpp b/src/V3Number.cpp
index 3a49a4897..0024d79aa 100644
--- a/src/V3Number.cpp
+++ b/src/V3Number.cpp
@@ -1177,8 +1177,8 @@ V3Number& V3Number::opModDivGuts(const V3Number& lhs, const V3Number& rhs, bool
     uint32_t vn[VL_MULS_MAX_WORDS+1]; // v normalized
 
     // Zero for ease of debugging and to save having to zero for shifts
-    for (int i=0; i<6; i++) { un[i]=vn[i]=m_value[i]=0; }
-    for (int i=6; i<words+1; i++) { un[i]=vn[i]=0; }  // +1 as vn may get extra word
+    for (int i=0; i<words; i++) { m_value[i]=0; }
+    for (int i=0; i<words+1; i++) { un[i]=vn[i]=0; }  // +1 as vn may get extra word
 
     // Algorithm requires divisor MSB to be set
     // Copy and shift to normalize divisor so MSB of vn[vw-1] is set