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Fix sampling of hierarchical references (#7386)

This commit is contained in:
Ryszard Rozak 2026-04-08 13:09:25 +02:00 committed by GitHub
parent 141fe8bdad
commit 7dcf586807
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GPG Key ID: B5690EEEBB952194
2 changed files with 3 additions and 4 deletions
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5
src/V3Assert.cpp
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@ -709,9 +709,8 @@ class AssertVisitor final : public VNVisitor {
} }
VL_DO_DANGLING(pushDeletep(nodep), nodep); VL_DO_DANGLING(pushDeletep(nodep), nodep);
} }
void visit(AstVarRef* nodep) override { void visit(AstNodeVarRef* nodep) override {
iterateChildren(nodep); if (m_inSampled && !nodep->varp()->noSample()) {
if (m_inSampled && !(nodep->varp() && nodep->varp()->noSample())) {
if (!nodep->access().isReadOnly()) { if (!nodep->access().isReadOnly()) {
nodep->v3warn(E_UNSUPPORTED, nodep->v3warn(E_UNSUPPORTED,
"Unsupported: Write to variable in sampled expression"); "Unsupported: Write to variable in sampled expression");

2
test_regress/t/t_property_disable_iff_midreset.v
View File

@ -24,7 +24,7 @@ module t (
int fails_b = 0; int fails_b = 0;
// First launch at cyc==2 should be canceled by reset pulse in the middle. // First launch at cyc==2 should be canceled by reset pulse in the middle.
assert property (@(posedge clk) disable iff (rst) (cyc == 2) |-> ##2 done) assert property (@(posedge clk) disable iff (rst) (t.cyc == 2) |-> ##2 done)
else fails_a++; else fails_a++;
// Second launch at cyc==8 has no reset pulse in flight and should fail once. // Second launch at cyc==8 has no reset pulse in flight and should fail once.