From 7dcf58680700616ea705fe12d1f5df020635d518 Mon Sep 17 00:00:00 2001 From: Ryszard Rozak Date: Wed, 8 Apr 2026 13:09:25 +0200 Subject: [PATCH] Fix sampling of hierarchical references (#7386) --- src/V3Assert.cpp | 5 ++--- test_regress/t/t_property_disable_iff_midreset.v | 2 +- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/src/V3Assert.cpp b/src/V3Assert.cpp index 87cd14f5b..2adda9d22 100644 --- a/src/V3Assert.cpp +++ b/src/V3Assert.cpp @@ -709,9 +709,8 @@ class AssertVisitor final : public VNVisitor { } VL_DO_DANGLING(pushDeletep(nodep), nodep); } - void visit(AstVarRef* nodep) override { - iterateChildren(nodep); - if (m_inSampled && !(nodep->varp() && nodep->varp()->noSample())) { + void visit(AstNodeVarRef* nodep) override { + if (m_inSampled && !nodep->varp()->noSample()) { if (!nodep->access().isReadOnly()) { nodep->v3warn(E_UNSUPPORTED, "Unsupported: Write to variable in sampled expression"); diff --git a/test_regress/t/t_property_disable_iff_midreset.v b/test_regress/t/t_property_disable_iff_midreset.v index e82e9ea46..c7972ee88 100644 --- a/test_regress/t/t_property_disable_iff_midreset.v +++ b/test_regress/t/t_property_disable_iff_midreset.v @@ -24,7 +24,7 @@ module t ( int fails_b = 0; // First launch at cyc==2 should be canceled by reset pulse in the middle. - assert property (@(posedge clk) disable iff (rst) (cyc == 2) |-> ##2 done) + assert property (@(posedge clk) disable iff (rst) (t.cyc == 2) |-> ##2 done) else fails_a++; // Second launch at cyc==8 has no reset pulse in flight and should fail once.