Support `$get_initial_random_seed` (#7056) (#7069).

Fixes #7056.

Changes

@@ -40,6 +40,7 @@ Verilator 5.045 devel
 * Support some system functions in constraint blocks (#7028) (#7036). [Yilou Wang]
 * Support std::randomize() for queue, dynamic array, and associative array variables (#7044). [Yilou Wang]
 * Support inherited and nested pre/post_randomize callbacks (#7049) (#7053). [Yilou Wang]
+* Support `$get_initial_random_seed` (#7056) (#7069). [Srinivasan Venkataramanan]
 * Remove deprecated `--xml-only`.
 * Remove deprecated `--make cmake`.
 * Change JSON dumps to not include booleans that are false (#6977).

docs/guide/extensions.rst

@@ -207,6 +207,14 @@ or "`ifdef`"'s may break other tools.
    5 digits per the C standard. This extension was standardized into
    1800-2009.
 
+.. option:: $get_initial_random_seed()
+
+   Returns an integer with the initial random seed used for the simulation.
+   This is the value provided via the :vlopt:`+verilator+seed+\<value\>`
+   runtime option. If no seed is specified, it returns the default
+   initialization seed (typically 0). This is not defined by IEEE
+   1800-2023, but most simulators support it.
+
 .. option:: $stacktrace
 
    Called as a task, print a stack trace. Called as a function, return a

src/V3AstNodeExpr.h

@@ -1616,6 +1616,24 @@ public:
     string emitC() override { V3ERROR_NA_RETURN(""); }
     bool cleanOut() const override { return true; }
 };
+class AstGetInitialRandomSeed final : public AstNodeExpr {
+    // Verilog $get_initial_random_seed()
+public:
+    explicit AstGetInitialRandomSeed(FileLine* fl)
+        : ASTGEN_SUPER_GetInitialRandomSeed(fl) {
+        dtypeSetSigned32();
+    }
+    ASTGEN_MEMBERS_AstGetInitialRandomSeed;
+    string emitVerilog() override { return "$get_initial_random_seed()"; }
+    string emitC() final override { V3ERROR_NA_RETURN(""); }
+    bool cleanOut() const override { return true; }
+    bool isGateOptimizable() const override { return false; }
+    bool isPredictOptimizable() const override { return true; }
+    bool isPure() override { return true; }
+    bool isSystemFunc() const override { return true; }
+    int instrCount() const override { return INSTR_COUNT_PLI; }
+    bool sameNode(const AstNode* /*samep*/) const override { return true; }
+};
 class AstImplication final : public AstNodeExpr {
     // Verilog Implication Operator
     // Nonoverlapped "|=>"

src/V3EmitCFunc.h

@@ -1341,6 +1341,9 @@ public:
                       / v3Global.rootp()->timeprecision().multiplier()));
         puts(")");
     }
+    void visit(AstGetInitialRandomSeed* nodep) override {
+        putns(nodep, "vlSymsp->_vm_contextp__->randSeed()");
+    }
     void visit(AstTimeFormat* nodep) override {
         putns(nodep, "VL_TIMEFORMAT_IINI(");
         if (nodep->unitsp()) {

src/V3Simulate.h

@@ -1368,6 +1368,7 @@ private:
         if (jumpingOver()) return;
         knownBadNodeType(nodep);
     }
+    void visit(AstGetInitialRandomSeed* nodep) override { badNodeType(nodep); }
     // ====
     // default
     // These types are definitely not reducible

src/V3Width.cpp

@@ -500,6 +500,7 @@ class WidthVisitor final : public VNVisitor {
     void visit(AstTime* nodep) override { nodep->dtypeSetUInt64(); }
     void visit(AstTimeD* nodep) override { nodep->dtypeSetDouble(); }
     void visit(AstTimePrecision* nodep) override { nodep->dtypeSetSigned32(); }
+    void visit(AstGetInitialRandomSeed* nodep) override { nodep->dtypeSetSigned32(); }
     void visit(AstTimeUnit* nodep) override {
         nodep->replaceWith(
             new AstConst{nodep->fileline(), AstConst::Signed32{}, nodep->timeunit().powerOfTen()});

src/verilog.l

@@ -528,6 +528,7 @@ vnum    {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
   "$fell"               { FL; return yD_FELL; }
   "$fell_gclk"          { FL; return yD_FELL_GCLK; }
   "$future_gclk"        { FL; return yD_FUTURE_GCLK; }
+  "$get_initial_random_seed" { FL; return yD_GET_INITIAL_RANDOM_SEED; }
   "$get_coverage"       { FL; STR; ERROR_RSVD_WORD("IEEE 1800-2005"); return yaD_PLI; }
   "$high"               { FL; return yD_HIGH; }
   "$increment"          { FL; return yD_INCREMENT; }

src/verilog.y

@@ -690,6 +690,7 @@ BISONPRE_VERSION(3.7,%define api.header.include {"V3ParseBison.h"})
 %token<fl>              yD_FWRITEB      "$fwriteb"
 %token<fl>              yD_FWRITEH      "$fwriteh"
 %token<fl>              yD_FWRITEO      "$fwriteo"
+%token<fl>              yD_GET_INITIAL_RANDOM_SEED "$get_initial_random_seed"
 %token<fl>              yD_GLOBAL_CLOCK "$global_clock"
 %token<fl>              yD_HIGH         "$high"
 %token<fl>              yD_HYPOT        "$hypot"
@@ -4458,6 +4459,7 @@ system_f_or_t_expr_call<nodeExprp>:  // IEEE: part of system_tf_call (can be tas
         |       yD_FSCANF '(' expr ',' str commaVRDListE ')'    { $$ = new AstFScanF{$1, *$5, $3, $6}; }
         |       yD_FSEEK '(' expr ',' expr ',' expr ')' { $$ = new AstFSeek{$1, $3, $5, $7}; }
         |       yD_FTELL '(' expr ')'                   { $$ = new AstFTell{$1, $3}; }
+        |       yD_GET_INITIAL_RANDOM_SEED parenE      { $$ = new AstGetInitialRandomSeed{$1}; }
         |       yD_GLOBAL_CLOCK parenE                  { $$ = GRAMMARP->createGlobalClockParseRef($1); }
         |       yD_HIGH '(' exprOrDataType ')'          { $$ = new AstAttrOf{$1, VAttrType::DIM_HIGH, $3, nullptr}; }
         |       yD_HIGH '(' exprOrDataType ',' expr ')' { $$ = new AstAttrOf{$1, VAttrType::DIM_HIGH, $3, $5}; }

test_regress/t/t_sys_get_init_seed.py

@@ -0,0 +1,20 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+
+test.lint(fails=False)
+
+test.compile(verilator_flags2=['--binary'])
+
+test.execute(all_run_flags=['+verilator+seed+22'])
+
+test.passes()

test_regress/t/t_sys_get_init_seed.v

@@ -0,0 +1,18 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain.
+// SPDX-FileCopyrightText: 2026 Srinivasan Venkataramanan
+// SPDX-License-Identifier: CC0-1.0
+
+module t;
+  int seed = 1;
+
+  initial begin
+    seed = $get_initial_random_seed();
+    $display("get_initial_random_seed=%0d", seed);
+    if (seed != 22) $stop;
+    $write("*-* All Finished *-*\n");
+    $finish(2);
+  end
+
+endmodule