diff --git a/src/V3AssertPre.cpp b/src/V3AssertPre.cpp
index 25c395139..92a4b46aa 100644
--- a/src/V3AssertPre.cpp
+++ b/src/V3AssertPre.cpp
@@ -161,14 +161,15 @@ private:
     void visit(AstModportClockingRef* const nodep) override {
         // It has to be converted to a list of ModportClockingVarRefs,
         // because clocking blocks are removed in this pass
-        for (AstClockingItem* itemp = nodep->clockingp()->itemsp(); itemp;
-             itemp = VN_AS(itemp->nextp(), ClockingItem)) {
-            AstVar* const varp = itemp->varp() ? itemp->varp() : VN_AS(itemp->user1p(), Var);
-            if (varp) {
-                AstModportVarRef* const modVarp
-                    = new AstModportVarRef{nodep->fileline(), varp->name(), itemp->direction()};
-                modVarp->varp(varp);
-                nodep->addNextHere(modVarp);
+        for (AstNode* itemp = nodep->clockingp()->itemsp(); itemp; itemp = itemp->nextp()) {
+            if (AstClockingItem* citemp = VN_CAST(itemp, ClockingItem)) {
+                if (AstVar* const varp
+                    = citemp->varp() ? citemp->varp() : VN_AS(citemp->user1p(), Var)) {
+                    AstModportVarRef* const modVarp = new AstModportVarRef{
+                        nodep->fileline(), varp->name(), citemp->direction()};
+                    modVarp->varp(varp);
+                    nodep->addNextHere(modVarp);
+                }
             }
         }
         VL_DO_DANGLING(pushDeletep(nodep->unlinkFrBack()), nodep);
diff --git a/src/V3AstNodeOther.h b/src/V3AstNodeOther.h
index 782f1a511..ece0c7ff5 100644
--- a/src/V3AstNodeOther.h
+++ b/src/V3AstNodeOther.h
@@ -765,15 +765,15 @@ class AstClocking final : public AstNode {
     // Parents:  MODULE
     // Children: SENITEM, CLOCKING ITEMs, VARs
     // @astgen op1 := sensesp : AstSenItem
-    // @astgen op2 := itemsp : List[AstClockingItem]
+    // @astgen op2 := itemsp : List[AstNode]
     // @astgen op3 := eventp : Optional[AstVar]
     std::string m_name;  // Clocking block name
     const bool m_isDefault;  // True if default clocking
     const bool m_isGlobal;  // True if global clocking
 
 public:
-    AstClocking(FileLine* fl, const std::string& name, AstSenItem* sensesp,
-                AstClockingItem* itemsp, bool isDefault, bool isGlobal)
+    AstClocking(FileLine* fl, const std::string& name, AstSenItem* sensesp, AstNode* itemsp,
+                bool isDefault, bool isGlobal)
         : ASTGEN_SUPER_Clocking(fl)
         , m_name{name}
         , m_isDefault{isDefault}
@@ -2347,6 +2347,22 @@ public:
     }
     string verilogKwd() const override { return "property"; }
 };
+class AstSequence final : public AstNodeFTask {
+    // A sequence inside a module
+    // TODO when supported might not want to be a NodeFTask
+    bool m_referenced = false;  // Ever referenced (for unsupported check)
+public:
+    AstSequence(FileLine* fl, const string& name, AstNode* stmtp)
+        : ASTGEN_SUPER_Sequence(fl, name, stmtp) {}
+    ASTGEN_MEMBERS_AstSequence;
+    bool hasDType() const override VL_MT_SAFE { return true; }
+    AstNodeFTask* cloneType(const string& name) override {
+        return new AstSequence{fileline(), name, nullptr};
+    }
+    string verilogKwd() const override { return "sequence"; }
+    bool isReferenced() const { return m_referenced; }
+    void isReferenced(bool flag) { m_referenced = flag; }
+};
 class AstTask final : public AstNodeFTask {
     // A task inside a module
 public:
diff --git a/src/V3LinkParse.cpp b/src/V3LinkParse.cpp
index 4bc6e8695..2c3b36a7f 100644
--- a/src/V3LinkParse.cpp
+++ b/src/V3LinkParse.cpp
@@ -931,28 +931,29 @@ class LinkParseVisitor final : public VNVisitor {
         VL_RESTORER(m_defaultInSkewp);
         VL_RESTORER(m_defaultOutSkewp);
         // Find default input and output skews
-        AstClockingItem* nextItemp = nodep->itemsp();
-        for (AstClockingItem* itemp = nextItemp; itemp; itemp = nextItemp) {
-            nextItemp = VN_AS(itemp->nextp(), ClockingItem);
-            if (itemp->exprp() || itemp->assignp()) continue;
-            if (itemp->skewp()) {
-                if (itemp->direction() == VDirection::INPUT) {
-                    // Disallow default redefinition; note some simulators allow this
-                    if (m_defaultInSkewp) {
-                        itemp->skewp()->v3error("Multiple default input skews not allowed");
+        for (AstNode *nextp, *itemp = nodep->itemsp(); itemp; itemp = nextp) {
+            nextp = itemp->nextp();
+            if (AstClockingItem* citemp = VN_CAST(itemp, ClockingItem)) {
+                if (citemp->exprp() || citemp->assignp()) continue;
+                if (citemp->skewp()) {
+                    if (citemp->direction() == VDirection::INPUT) {
+                        // Disallow default redefinition; note some simulators allow this
+                        if (m_defaultInSkewp) {
+                            citemp->skewp()->v3error("Multiple default input skews not allowed");
+                        }
+                        m_defaultInSkewp = citemp->skewp();
+                    } else if (citemp->direction() == VDirection::OUTPUT) {
+                        // Disallow default redefinition; note some simulators allow this
+                        if (m_defaultOutSkewp) {
+                            citemp->skewp()->v3error("Multiple default output skews not allowed");
+                        }
+                        m_defaultOutSkewp = citemp->skewp();
+                    } else {
+                        citemp->v3fatalSrc("Incorrect direction");
                     }
-                    m_defaultInSkewp = itemp->skewp();
-                } else if (itemp->direction() == VDirection::OUTPUT) {
-                    // Disallow default redefinition; note some simulators allow this
-                    if (m_defaultOutSkewp) {
-                        itemp->skewp()->v3error("Multiple default output skews not allowed");
-                    }
-                    m_defaultOutSkewp = itemp->skewp();
-                } else {
-                    itemp->v3fatalSrc("Incorrect direction");
                 }
+                VL_DO_DANGLING(pushDeletep(citemp->unlinkFrBack()), citemp);
             }
-            VL_DO_DANGLING(pushDeletep(itemp->unlinkFrBack()), itemp);
         }
         iterateChildren(nodep);
     }
diff --git a/src/V3LinkResolve.cpp b/src/V3LinkResolve.cpp
index f362d8bb7..ad6d72d3e 100644
--- a/src/V3LinkResolve.cpp
+++ b/src/V3LinkResolve.cpp
@@ -188,6 +188,10 @@ class LinkResolveVisitor final : public VNVisitor {
     }
     void visit(AstNodeFTaskRef* nodep) override {
         VL_RESTORER(m_currentRandomizeSelectp);
+        if (nodep->taskp()) {
+            if (AstSequence* const seqp = VN_CAST(nodep->taskp(), Sequence))
+                seqp->isReferenced(true);
+        }
 
         if (nodep->name() == "randomize") {
             if (const AstMethodCall* const methodcallp = VN_CAST(nodep, MethodCall)) {
diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index a9d8b3bfe..77149051b 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -3469,10 +3469,12 @@ class WidthVisitor final : public VNVisitor {
     AstVar* memberSelClocking(AstMemberSel* nodep, AstClocking* clockingp) {
         // Returns node if ok
         VSpellCheck speller;
-        for (AstClockingItem* itemp = clockingp->itemsp(); itemp;
-             itemp = VN_AS(itemp->nextp(), ClockingItem)) {
-            if (itemp->varp()->name() == nodep->name()) return itemp->varp();
-            speller.pushCandidate(itemp->varp()->prettyName());
+
+        for (AstNode* itemp = clockingp->itemsp(); itemp; itemp = itemp->nextp()) {
+            if (AstClockingItem* citemp = VN_CAST(itemp, ClockingItem)) {
+                if (citemp->varp()->name() == nodep->name()) return citemp->varp();
+                speller.pushCandidate(citemp->varp()->prettyName());
+            }
         }
         const string suggest = speller.bestCandidateMsg(nodep->prettyName());
         nodep->v3error(
@@ -6462,6 +6464,15 @@ class WidthVisitor final : public VNVisitor {
         nodep->doingWidth(false);
     }
     void visit(AstReturn* nodep) override { nodep->v3fatalSrc("'return' missed in LinkJump"); }
+    void visit(AstSequence* nodep) override {
+        // UNSUPPORTED message is thrown only where the sequence is referenced
+        // in order to enable some UVM tests.
+        // When support more here will need finer-grained UNSUPPORTED if items
+        // under the sequence are not supported
+        if (nodep->isReferenced()) nodep->v3warn(E_UNSUPPORTED, "Unsupported: sequence");
+        userIterateChildren(nodep, nullptr);
+        if (!nodep->isReferenced()) VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep);
+    }
 
     AstPackage* getItemPackage(AstNode* pkgItemp) {
         while (pkgItemp->backp() && pkgItemp->backp()->nextp() == pkgItemp) {
diff --git a/src/verilog.y b/src/verilog.y
index 3fc6e4563..176d7df87 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -6127,17 +6127,17 @@ clocking_event<senItemp>:       // IEEE: clocking_event
         |       '@' '(' event_expression ')'            { $$ = $3; }
         ;
 
-clocking_itemListE<clockingItemp>:
+clocking_itemListE<nodep>:
                 /* empty */                             { $$ = nullptr; }
         |       clocking_itemList                       { $$ = $1; }
         ;
 
-clocking_itemList<clockingItemp>:  // IEEE: [ clocking_item ]
+clocking_itemList<nodep>:  // IEEE: [ clocking_item ]
                 clocking_item                           { $$ = $1; }
         |       clocking_itemList clocking_item         { if ($1) $$ = addNextNull($1, $2); }
         ;
 
-clocking_item<clockingItemp>:   // IEEE: clocking_item
+clocking_item<nodep>:   // IEEE: clocking_item
                 yDEFAULT yINPUT clocking_skew ';'       { $$ = new AstClockingItem{$<fl>1, VDirection::INPUT, $3, nullptr}; }
         |       yDEFAULT yOUTPUT clocking_skew ';'      { $$ = new AstClockingItem{$<fl>1, VDirection::OUTPUT, $3, nullptr}; }
         |       yDEFAULT yINPUT clocking_skew yOUTPUT clocking_skew ';'
@@ -6154,8 +6154,16 @@ clocking_item<clockingItemp>:   // IEEE: clocking_item
                         { $$ = GRAMMARP->makeClockingItemList($<fl>1, VDirection::INPUT, nullptr, $2->cloneTree(true));
                           $$->addNext(GRAMMARP->makeClockingItemList($<fl>1, VDirection::OUTPUT, nullptr, $2)); }
         |       assertion_item_declaration
-                        { $$ = nullptr;
-                          BBUNSUP($1, "Unsupported: assertion items in clocking blocks"); DEL($1); }
+                        { $$ = $1;
+                          for (AstNode* nodep = $1; nodep; nodep = nodep->nextp()) {
+                              if (!VN_IS(nodep, Sequence)) {
+                                  $$ = nullptr;
+                                  BBUNSUP(nodep, "Unsupported: assertion items in clocking blocks");
+                                  DEL($1);
+                                  break;
+                              }
+                          }
+                        }
         ;
 
 list_of_clocking_decl_assign<nodep>:  // IEEE: list_of_clocking_decl_assign
@@ -6395,13 +6403,16 @@ sequence_declaration<nodeFTaskp>:  // ==IEEE: sequence_declaration
                         { $$ = $1;
                           $$->addStmtsp($2);
                           $$->addStmtsp($4);
-                          GRAMMARP->endLabel($<fl>6, $$, $6); }
+                          GRAMMARP->endLabel($<fl>6, $$, $6);
+                          // No error on UVM special case with no reference; see t_sequence_unused.v
+                          if (! (!$$->stmtsp() || (VN_IS($$->stmtsp(), Const) && !$$->stmtsp()->nextp())))
+                              $$->v3warn(E_UNSUPPORTED, "Unsupported: sequence");
+                        }
         ;
 
 sequence_declarationFront<nodeFTaskp>:  // IEEE: part of sequence_declaration
                 ySEQUENCE idAny/*new_sequence*/
-                        { BBUNSUP($1, "Unsupported: sequence");
-                          $$ = new AstProperty{$<fl>2, *$2, nullptr}; }
+                        { $$ = new AstSequence{$<fl>2, *$2, nullptr}; }
         ;
 
 sequence_port_listE<nodep>:  // IEEE: [ ( [ sequence_port_list ] ) ]
diff --git a/test_regress/t/t_sequence_ref_unsup.out b/test_regress/t/t_sequence_ref_unsup.out
new file mode 100644
index 000000000..414375621
--- /dev/null
+++ b/test_regress/t/t_sequence_ref_unsup.out
@@ -0,0 +1,6 @@
+%Error-UNSUPPORTED: t/t_sequence_ref_unsup.v:9:12: Unsupported: sequence
+                                                 : ... note: In instance 't'
+    9 |   sequence s_one;
+      |            ^~~~~
+                    ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
+%Error: Exiting due to
diff --git a/test_regress/t/t_sequence_ref_unsup.py b/test_regress/t/t_sequence_ref_unsup.py
new file mode 100755
index 000000000..d529bbc7a
--- /dev/null
+++ b/test_regress/t/t_sequence_ref_unsup.py
@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+
+test.lint(expect_filename=test.golden_filename, verilator_flags2=['--timing'], fails=True)
+
+test.passes()
diff --git a/test_regress/t/t_sequence_ref_unsup.v b/test_regress/t/t_sequence_ref_unsup.v
new file mode 100644
index 000000000..32b86a3d5
--- /dev/null
+++ b/test_regress/t/t_sequence_ref_unsup.v
@@ -0,0 +1,19 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2023 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t;
+
+  sequence s_one;
+    1;
+  endsequence
+
+  initial begin
+    @s_one;
+    $display("got sequence");
+    $finish;
+  end
+
+endmodule
diff --git a/test_regress/t/t_sequence_sexpr_unsup.out b/test_regress/t/t_sequence_sexpr_unsup.out
index 6f1065b80..a6c63030e 100644
--- a/test_regress/t/t_sequence_sexpr_unsup.out
+++ b/test_regress/t/t_sequence_sexpr_unsup.out
@@ -1,175 +1,175 @@
-%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:27:4: Unsupported: sequence
+%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:27:13: Unsupported: sequence
    27 |    sequence s_a;
-      |    ^~~~~~~~
+      |             ^~~
                     ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
-%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:30:4: Unsupported: sequence
+%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:30:13: Unsupported: sequence
    30 |    sequence s_var;
-      |    ^~~~~~~~
-%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:35:4: Unsupported: sequence
-   35 |    sequence s_within;
-      |    ^~~~~~~~
+      |             ^~~~~
 %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:36:9: Unsupported: within (in sequence expression)
    36 |       a within(b);
       |         ^~~~~~
-%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:39:4: Unsupported: sequence
-   39 |    sequence s_and;
-      |    ^~~~~~~~
+%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:35:13: Unsupported: sequence
+   35 |    sequence s_within;
+      |             ^~~~~~~~
 %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:40:9: Unsupported: and (in sequence expression)
    40 |       a and b;
       |         ^~~
-%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:43:4: Unsupported: sequence
-   43 |    sequence s_or;
-      |    ^~~~~~~~
+%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:39:13: Unsupported: sequence
+   39 |    sequence s_and;
+      |             ^~~~~
 %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:44:9: Unsupported: or (in sequence expression)
    44 |       a or b;
       |         ^~
-%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:47:4: Unsupported: sequence
-   47 |    sequence s_throughout;
-      |    ^~~~~~~~
+%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:43:13: Unsupported: sequence
+   43 |    sequence s_or;
+      |             ^~~~
 %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:48:9: Unsupported: throughout (in sequence expression)
    48 |       a throughout b;
       |         ^~~~~~~~~~
-%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:51:4: Unsupported: sequence
-   51 |    sequence s_intersect;
-      |    ^~~~~~~~
+%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:47:13: Unsupported: sequence
+   47 |    sequence s_throughout;
+      |             ^~~~~~~~~~~~
 %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:52:9: Unsupported: intersect (in sequence expression)
    52 |       a intersect b;
       |         ^~~~~~~~~
-%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:55:4: Unsupported: sequence
+%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:51:13: Unsupported: sequence
+   51 |    sequence s_intersect;
+      |             ^~~~~~~~~~~
+%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:55:13: Unsupported: sequence
    55 |    sequence s_uni_cycdelay_id;
-      |    ^~~~~~~~
-%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:58:4: Unsupported: sequence
+      |             ^~~~~~~~~~~~~~~~~
+%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:58:13: Unsupported: sequence
    58 |    sequence s_uni_cycdelay_pid;
-      |    ^~~~~~~~
-%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:61:4: Unsupported: sequence
-   61 |    sequence s_uni_cycdelay_range;
-      |    ^~~~~~~~
+      |             ^~~~~~~~~~~~~~~~~~
 %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:62:7: Unsupported: ## range cycle delay range expression
    62 |       ## [1:2] b;
       |       ^~
-%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:64:4: Unsupported: sequence
-   64 |    sequence s_uni_cycdelay_star;
-      |    ^~~~~~~~
+%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:61:13: Unsupported: sequence
+   61 |    sequence s_uni_cycdelay_range;
+      |             ^~~~~~~~~~~~~~~~~~~~
 %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:65:7: Unsupported: ## [*] cycle delay range expression
    65 |       ## [*] b;
       |       ^~
-%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:67:4: Unsupported: sequence
-   67 |    sequence s_uni_cycdelay_plus;
-      |    ^~~~~~~~
+%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:64:13: Unsupported: sequence
+   64 |    sequence s_uni_cycdelay_star;
+      |             ^~~~~~~~~~~~~~~~~~~
 %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:68:7: Unsupported: ## [+] cycle delay range expression
    68 |       ## [+] b;
       |       ^~
-%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:71:4: Unsupported: sequence
+%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:67:13: Unsupported: sequence
+   67 |    sequence s_uni_cycdelay_plus;
+      |             ^~~~~~~~~~~~~~~~~~~
+%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:71:13: Unsupported: sequence
    71 |    sequence s_cycdelay_id;
-      |    ^~~~~~~~
-%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:74:4: Unsupported: sequence
+      |             ^~~~~~~~~~~~~
+%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:74:13: Unsupported: sequence
    74 |    sequence s_cycdelay_pid;
-      |    ^~~~~~~~
-%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:77:4: Unsupported: sequence
-   77 |    sequence s_cycdelay_range;
-      |    ^~~~~~~~
+      |             ^~~~~~~~~~~~~~
 %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:78:9: Unsupported: ## range cycle delay range expression
    78 |       a ## [1:2] b;
       |         ^~
-%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:80:4: Unsupported: sequence
-   80 |    sequence s_cycdelay_star;
-      |    ^~~~~~~~
+%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:77:13: Unsupported: sequence
+   77 |    sequence s_cycdelay_range;
+      |             ^~~~~~~~~~~~~~~~
 %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:81:9: Unsupported: ## [*] cycle delay range expression
    81 |       a ## [*] b;
       |         ^~
-%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:83:4: Unsupported: sequence
-   83 |    sequence s_cycdelay_plus;
-      |    ^~~~~~~~
+%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:80:13: Unsupported: sequence
+   80 |    sequence s_cycdelay_star;
+      |             ^~~~~~~~~~~~~~~
 %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:84:9: Unsupported: ## [+] cycle delay range expression
    84 |       a ## [+] b;
       |         ^~
-%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:87:4: Unsupported: sequence
-   87 |    sequence s_booleanabbrev_brastar_int;
-      |    ^~~~~~~~
+%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:83:13: Unsupported: sequence
+   83 |    sequence s_cycdelay_plus;
+      |             ^~~~~~~~~~~~~~~
 %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:88:9: Unsupported: [*] boolean abbrev expression
    88 |       a [* 1 ];
       |         ^~
 %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:88:12: Unsupported: boolean abbrev (in sequence expression)
    88 |       a [* 1 ];
       |            ^
-%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:90:4: Unsupported: sequence
-   90 |    sequence s_booleanabbrev_brastar;
-      |    ^~~~~~~~
+%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:87:13: Unsupported: sequence
+   87 |    sequence s_booleanabbrev_brastar_int;
+      |             ^~~~~~~~~~~~~~~~~~~~~~~~~~~
 %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:91:9: Unsupported: [*] boolean abbrev expression
    91 |       a [*];
       |         ^~
 %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:91:9: Unsupported: boolean abbrev (in sequence expression)
    91 |       a [*];
       |         ^~
-%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:93:4: Unsupported: sequence
-   93 |    sequence s_booleanabbrev_plus;
-      |    ^~~~~~~~
+%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:90:13: Unsupported: sequence
+   90 |    sequence s_booleanabbrev_brastar;
+      |             ^~~~~~~~~~~~~~~~~~~~~~~
 %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:94:9: Unsupported: [+] boolean abbrev expression
    94 |       a [+];
       |         ^~~
 %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:94:9: Unsupported: boolean abbrev (in sequence expression)
    94 |       a [+];
       |         ^~~
-%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:96:4: Unsupported: sequence
-   96 |    sequence s_booleanabbrev_eq;
-      |    ^~~~~~~~
+%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:93:13: Unsupported: sequence
+   93 |    sequence s_booleanabbrev_plus;
+      |             ^~~~~~~~~~~~~~~~~~~~
 %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:97:9: Unsupported: [= boolean abbrev expression
    97 |       a [= 1];
       |         ^~
 %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:97:12: Unsupported: boolean abbrev (in sequence expression)
    97 |       a [= 1];
       |            ^
-%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:99:4: Unsupported: sequence
-   99 |    sequence s_booleanabbrev_eq_range;
-      |    ^~~~~~~~
+%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:96:13: Unsupported: sequence
+   96 |    sequence s_booleanabbrev_eq;
+      |             ^~~~~~~~~~~~~~~~~~
 %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:100:9: Unsupported: [= boolean abbrev expression
   100 |       a [= 1:2];
       |         ^~
 %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:100:12: Unsupported: boolean abbrev (in sequence expression)
   100 |       a [= 1:2];
       |            ^
-%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:102:4: Unsupported: sequence
-  102 |    sequence s_booleanabbrev_minusgt;
-      |    ^~~~~~~~
+%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:99:13: Unsupported: sequence
+   99 |    sequence s_booleanabbrev_eq_range;
+      |             ^~~~~~~~~~~~~~~~~~~~~~~~
 %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:103:9: Unsupported: [-> boolean abbrev expression
   103 |       a [-> 1];
       |         ^~~
 %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:103:13: Unsupported: boolean abbrev (in sequence expression)
   103 |       a [-> 1];
       |             ^
-%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:105:4: Unsupported: sequence
-  105 |    sequence s_booleanabbrev_minusgt_range;
-      |    ^~~~~~~~
+%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:102:13: Unsupported: sequence
+  102 |    sequence s_booleanabbrev_minusgt;
+      |             ^~~~~~~~~~~~~~~~~~~~~~~
 %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:106:9: Unsupported: [-> boolean abbrev expression
   106 |       a [-> 1:2];
       |         ^~~
 %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:106:13: Unsupported: boolean abbrev (in sequence expression)
   106 |       a [-> 1:2];
       |             ^
-%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:109:4: Unsupported: sequence
-  109 |    sequence p_arg_seqence(sequence inseq);
-      |    ^~~~~~~~
+%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:105:13: Unsupported: sequence
+  105 |    sequence s_booleanabbrev_minusgt_range;
+      |             ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:109:27: Unsupported: sequence argument data type
   109 |    sequence p_arg_seqence(sequence inseq);
       |                           ^~~~~~~~
-%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:113:4: Unsupported: sequence
-  113 |    sequence s_firstmatch_a;
-      |    ^~~~~~~~
+%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:109:13: Unsupported: sequence
+  109 |    sequence p_arg_seqence(sequence inseq);
+      |             ^~~~~~~~~~~~~
 %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:114:7: Unsupported: first_match (in sequence expression)
   114 |       first_match (a);
       |       ^~~~~~~~~~~
-%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:116:4: Unsupported: sequence
-  116 |    sequence s_firstmatch_ab;
-      |    ^~~~~~~~
+%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:113:13: Unsupported: sequence
+  113 |    sequence s_firstmatch_a;
+      |             ^~~~~~~~~~~~~~
 %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:117:7: Unsupported: first_match (in sequence expression)
   117 |       first_match (a, res0 = 1);
       |       ^~~~~~~~~~~
-%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:119:4: Unsupported: sequence
-  119 |    sequence s_firstmatch_abc;
-      |    ^~~~~~~~
+%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:116:13: Unsupported: sequence
+  116 |    sequence s_firstmatch_ab;
+      |             ^~~~~~~~~~~~~~~
 %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:120:7: Unsupported: first_match (in sequence expression)
   120 |       first_match (a, res0 = 1, res1 = 2);
       |       ^~~~~~~~~~~
+%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:119:13: Unsupported: sequence
+  119 |    sequence s_firstmatch_abc;
+      |             ^~~~~~~~~~~~~~~~
 %Warning-COVERIGN: t/t_sequence_sexpr_unsup.v:123:10: Ignoring unsupported: cover sequence
   123 |    cover sequence (s_a) $display("");
       |          ^~~~~~~~
diff --git a/test_regress/t/t_sequence_unused.py b/test_regress/t/t_sequence_unused.py
new file mode 100755
index 000000000..f989a35fb
--- /dev/null
+++ b/test_regress/t/t_sequence_unused.py
@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile()
+
+test.execute()
+
+test.passes()
diff --git a/test_regress/t/t_sequence_unused.v b/test_regress/t/t_sequence_unused.v
new file mode 100644
index 000000000..0d57ea468
--- /dev/null
+++ b/test_regress/t/t_sequence_unused.v
@@ -0,0 +1,34 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+interface apb_if (
+    input bit clk
+);
+  wire [31:0] paddr;
+  wire [31:0] prdata;
+
+  clocking mck @(posedge clk);
+    output paddr;
+    input prdata;
+
+    // Some UVM tests declare this sequence but never use it
+    // so we defer UNSUPPORTED until usage point
+    sequence at_posedge;
+      1;
+    endsequence : at_posedge
+  endclocking
+
+endinterface
+
+module t (
+    input clk
+  );
+
+  apb_if ifc(clk);
+
+  initial $finish;
+
+endmodule